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参数资料
| 型号： | MPC8572PXAULB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023 |
| 封装： | 33 X 33 MM, PLASTIC, FCBGA-1023 |
| 文件页数： | 51/138页 |
| 文件大小： | 1502K |
| 代理商： | MPC8572PXAULB |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
2
Freescale Semiconductor
Overview
— Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive
instruction set for vector (64-bit) integer and fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions.
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
— 36-bit real addressing
— Memory management unit (MMU). Especially designed for embedded applications. Supports
4-Kbyte–4-Gbyte page sizes.
— Enhanced hardware and software debug support
— Performance monitor facility that is similar to, but separate from, the MPC8572E performance
monitor
The e500 defines features that are not implemented on this device. It also generally defines some
features that this device implements more specifically. An understanding of these differences can
be critical to ensure proper operation.
1 Mbyte L2 cache/SRAM
— Shared by both cores.
— Flexible configuration and individually configurable per core.
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
– 1, 2, or 4 ways can be configured for stashing only.
— Eight-way set-associative cache organization (32-byte cache lines)
— Supports locking entire cache or selected lines. Individual line locks are set and cleared through
Book E instructions or by externally mastered transactions.
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately.
— Per-way allocation of cache region to a given processor.
— SRAM features include the following:
– 1, 2, 4, or 8 ways can be configured as SRAM.
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
smaller-than-cache-line accesses.
e500 coherency module (ECM) manages core and intra-system transactions
Address translation and mapping unit (ATMU)
— Twelve local access windows define mapping within local 36-bit address space.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8572PXAULD | 功能描述:微处理器 - MPU PQ38H CSM SNPB 1333 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572PXAULE | 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1333 - Bulk |
| MPC8572PXAVNB | 功能描述:微处理器 - MPU RV1.1.1 SNPB 1500 NOTENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572PXAVND | 功能描述:微处理器 - MPU PQ38H CSM SNPB 1500 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572PXAVNE | 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1500 - Bulk |
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