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参数资料
型号： MPC8572PXAULB
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
封装： 33 X 33 MM, PLASTIC, FCBGA-1023
文件页数： 64/138页
文件大小： 1502K
代理商： MPC8572PXAULB
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
31
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this
section.
8.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI
specifications, since they have similar performance and are described in a source-synchronous fashion like
FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back on
the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended
that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-
synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock
is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is a relationship
between the maximum FIFO speed and the platform (CCB) frequency. For more information see
Section 4.5, “Platform to eTSEC FIFO Restrictions.”
Table 24 and Table 25 summarize the FIFO AC specifications.
Input high current
(VIN = LVDD, VIN = TVDD)
IIH
—10
μA
1, 2,3
Input low current
(VIN = GND)
IIL
–15
—
μA
3
Note:
1 LV
DD supports eTSECs 1 and 2.
2 TV
DD supports eTSECs 3 and 4 or FEC.
3 Note that the symbol V
IN, in this case, represents the LVIN and TVIN symbols referenced in Table 1.
Table 24. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TX_CLK, GTX_CLK clock period1
tFIT
5.3
8.0
100
ns
TX_CLK, GTX_CLK duty cycle
tFITH/tFIT
45
50
55
%
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
——
250
ps
Table 23. MII, GMII, RMII, RGMII, TBI, RTBI, and FIFO DC Electrical Characteristics (continued)
Parameters
Symbol
Min
Max
Unit
Notes
相关PDF资料
PDF描述
MPC8572CPXAUND 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
MPC8572ECPXAUNB 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
MPC8572VTAVLD 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
MPC8572CVTAULD 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
MPC8572EVTATND 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA1023
相关代理商/技术参数
参数描述
MPC8572PXAULD 功能描述:微处理器 - MPU PQ38H CSM SNPB 1333 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8572PXAULE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1333 - Bulk
MPC8572PXAVNB 功能描述:微处理器 - MPU RV1.1.1 SNPB 1500 NOTENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8572PXAVND 功能描述:微处理器 - MPU PQ38H CSM SNPB 1500 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8572PXAVNE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1500 - Bulk
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