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| 型号： | MPC9229EI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | IC CLK SYNTH LV PECL 28-PLCC |
| 标准包装： | 37 |
| 类型： | 时钟/频率合成器 |
| PLL： | 带旁路 |
| 输入： | 晶体 |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC（11.5x11.5） |
| 包装： | 管件 |
MPC9229 REVISION 5 DECEMBER 19, 2012
3
2012 Integrated Device Technology, Inc.
MPC9229 Data Sheet
400MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
Table 1. Pin Configurations
Pin
I/O
Default
Type
Function
XTAL_IN, XTAL_OUT
—
Analog
Crystal oscillator interface
fOUT, fOUT
Output
—
LVPECL
Differential clock output
TEST
Output
—
LVCMOS
Test and device diagnosis output
S_LOAD
Input
0
LVCMOS
Serial configuration control input
This inputs controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition
P_LOAD
Input
1
LVCMOS
Parallel configuration control input
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low, thus
the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is
state sensitive
S_DATA
Input
0
LVCMOS
Serial configuration data input
S_CLOCK
Input
0
LVCMOS
Serial configuration clock input
M[0:8]
Input
1
LVCMOS
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
Input
1
LVCMOS
Parallel configuration for Post-PLL divider (N)
N is sampled on the low-to-high transition of P_LOAD
OE
Input
1
LVCMOS
Output enable (active high).
The output enable is synchronous to the output clock to eliminate the possibility of runt
pulses on the fOUT output. OE = L low stops fOUT in the logic low state (fOUT = L, fOUT
= H)
GND
Supply
Ground
Negative power supply (GND).
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to
the positive power supply for correct operation.
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply).
Table 2. Output Frequency Range and Pll Post-Divider N
N
Output Division
Output Frequency Range
1
0
0
1
200 – 400 MHz
0
1
2
100 – 200 MHz
1
0
4
50 – 100 MHz
1
8
25 – 50 MHz
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