- 您现在的位置：买卖IC网 > PDF目录2099 > MPC9350AC (IDT, Integrated Device Technology Inc)IC PLL CLOCK DRIVER LV 32-LQFP PDF资料下载
参数资料
| 型号： | MPC9350AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK DRIVER LV 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:9 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
DATASHEET
Low Voltage PLL Clock Driver
MPC9350
NRND
MPC9350 REVISION 7 DECEMBER 19, 2012
1
2012 Integrated Device Technology, Inc.
Low Voltage PLL Clock Driver
The MPC9350 is a 2.5 V and 3.3 V compatible, PLL-based clock generator
targeted for high performance clock distribution systems. With output
frequencies of up to 200 MHz and maximum output skews of 150 ps, the
MPC9350 is ideal for the most demanding clock tree designs. The device offers
9 low skew clock outputs, with each one configurable to support the clocking
needs of the various high-performance microprocessors, including the
PowerQUICC II integrated communication microprocessor. The extended
temperature range of the MPC9350 supports telecommunication and networking
requirements. The device employs a fully differential PLL design to minimize
cycle-to-cycle and long-term jitter.
Features
9 Output LVCMOS PLL Clock Generator
25 – 200 MHz Output Frequency Range
2.5 V and 3.3 V Compatible
Compatible to Various Microprocessors Such as PowerQuicc II
Supports Networking,Telecommunications and Computer Applications
Fully Integrated PLL
Configurable Outputs: Divide-by-2, 4 and 8 of VCO Frequency
Selectable Output to Input Frequency Ratio of 8:1, 4:1, 2:1 or 1:1
Oscillator or Crystal Reference Inputs
Internal PLL Feedback
Output Disable
PLL Enable/Disable
Low Skew Characteristics: Maximum 150 ps Output-to-Output
32-Lead LQFP Package, Pb-Free
Temperature Range –40
C to +85C
Functional Description
The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference
clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference
clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable
PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects
between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match
the VCO frequency range. With the available feedback output dividers, the internal VCO of the MPC9350 is running at either 16x
or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one
eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD
pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal
oscillator input or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode
when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly
to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purposes. This
test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by
deasserting the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path.
The MPC9350 is fully 2.5 V and 3.3 V compatible and requires no external loop filter components. The on-chip crystal oscillator
requires no external components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission
lines. For series terminated transmission lines, each of the MPC9350 outputs can drive one or two traces giving the device an
effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package.
MPC9350
LOW VOLTAGE
3.3 V AND 2.5 V PLL
CLOCK GENERATOR
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
NRND – Not Recommend for New Designs
相关PDF资料 |
PDF描述 |
|---|---|
| MPC941AE | IC CLOCK BUFFER MUX 1:27 48-LQFP |
| MPC9443FAR2 | IC CLK BUFF DVDR MUX 3:16 48LQFP |
| MPC9446FAR2 | IC CLK BUFF DVDR MUX 2:10 32LQFP |
| MPC9447ACR2 | IC CLOCK BUFFER MUX 2:9 32-LQFP |
| MPC9448ACR2 | IC CLOCK BUFFER MUX 1:12 32-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9350ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9350D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350FA | 功能描述:时钟驱动器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC9350FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC9351 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Low Voltage PLL Clock Driver |
发布紧急采购，3分钟左右您将得到回复。