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参数资料
| 型号： | MPC9350AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK DRIVER LV 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:9 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9350 REVISION 7 DECEMBER 19, 2012
7
2012 Integrated Device Technology, Inc.
MPC9350 Data Sheet
Low Voltage PLL Clock Driver
Power Supply Filtering
The MPC9350 is a mixed analog/digital product and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC9350 provides separate
power supplies for the output buffers (VCCO) and the
phase-locked loop (VCCA) of the device.
The purpose of this design technique is to try and isolate
the high switching noise digital outputs from the relatively
sensitive internal analog phase-locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient; however, in a digital system
environment where it is more difficult to minimize noise on the
power supplies, a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
power supply filter scheme. The MPC9350 is most
susceptible to noise with spectral content in the 10 kHz to
5 MHz range; therefore, the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop that will be seen
between the VCC supply and the VCCA pin of the MPC9350.
From the data sheet the IVCCA current (the current sourced
through the VCCA pin) is typically 10 mA (15 mA maximum),
assuming that a minimum of 3.0 V must be maintained on the
VCCA pin. Very little DC voltage drop can be tolerated when a
must have a resistance of 10–15
to meet the voltage drop
criteria for VCC = 3.3 V. For VCC = 2.5 V operation, RS must
be selected to maintain the minimum VCC specification of
2.375 V for the PLL supply pin for proper operation. The RC
filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the
series resonant point of an individual capacitor, its overall
impedance begins to look inductive and, thus, increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL. It is
recommended that the user start with an 8–10
resistor to
avoid potential VCC drop problems and only move to the
higher value resistors when a higher level of attenuation is
shown to be needed.
Figure 3. Power Supply Filter
Although the MPC9350 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems in
most designs.
Driving Transmission Lines
The MPC9350 clock driver was designed to drive high-
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 15
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC2.
This technique draws a fairly high level of DC current, and
thus, only a single terminated line can be driven by each
output of the MPC9350 clock driver. For the series terminated
case, however, there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 4 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9350 clock driver is effectively doubled
due to its capability to drive multiple lines.
Figure 4. Single versus Dual Transmission Lines
The waveform plots in Figure 5 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9350 output buffer
is more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
VCCA
VCC
MPC9350
0.01
F
22
F
0.01
F
2.5V or 3.3V
RS=5–15
14
IN
MPC9350
Output
Buffer
RS = 36
ZO = 50
OutA
14
IN
MPC9350
Output
Buffer
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9350ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9350D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350FA | 功能描述:时钟驱动器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC9350FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC9351 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Low Voltage PLL Clock Driver |
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