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参数资料
| 型号： | MPC9350AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK DRIVER LV 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:9 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9350 REVISION 7 DECEMBER 19, 2012
6
2012 Integrated Device Technology, Inc.
MPC9350 Data Sheet
Low Voltage PLL Clock Driver
APPLICATIONS INFORMATION
Programming the MPC9350
The MPC9350 clock driver outputs can be configured into
several divider modes. In addition, the internal feedback of
the device allows for flexibility in establishing two input to
output frequency relationships. The output division settings
establish the output frequency relationship. The output
divider of the four output groups allows the user to configure
the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The
use of even dividers ensures that the output duty cycle is
configurations. The tables describe the outputs using the
input clock frequency CLK as a reference.
In addition, it must be ensured that the VCO will be stable
given the frequency of the outputs desired. The feedback
frequency should be used to situate the VCO into a frequency
range in which the PLL will be stable. The design of the PLL
supports output frequencies from 25 MHz to 200 MHz while
the VCO frequency range is specified from 200 MHz to
400 MHz and should not be exceeded for stable operation.
Table 7. Output Frequency Relationship(1) FBSEL = 0, (VC0 = 32 * CLK)
1. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 data sheet for more input to output
relationships in external feedback mode.
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC0, QC1
QD0–QD4
0
16 * CLK
8 * CLK
0
1
16 * CLK
8 * CLK
4 * CLK
0
1
0
16 * CLK
8 * CLK
4 * CLK
8 * CLK
0
1
16 * CLK
8 * CLK
4 * CLK
0
1
0
16 * CLK
4 * CLK
8 * CLK
0
1
0
1
16 * CLK
4 * CLK
8 * CLK
4 * CLK
0
1
0
16 * CLK
4 * CLK
8 * CLK
0
1
16 * CLK
4 * CLK
1
0
8 * CLK
1
0
1
8 * CLK
4 * CLK
1
0
1
0
8 * CLK
4 * CLK
8 * CLK
1
0
1
8 * CLK
4 * CLK
1
0
8 * CLK
4 * CLK
8 * CLK
1
0
1
8 * CLK
4 * CLK
8 * CLK
4 * CLK
1
0
8 * CLK
4 * CLK
8 * CLK
1
8 * CLK
4 * CLK
Table 8. Output Frequency Relationship(1) FBSEL = 1, (VC0 = 16 * CLK)
1. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 data sheet for more input to output
relationships in external feedback mode.
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC0, QC1
QD0–QD4
0
8 * CLK
4 * CLK
0
1
8 * CLK
4 * CLK
2 * CLK
0
1
0
8 * CLK
4 * CLK
2 * CLK
4 * CLK
0
1
8 * CLK
4 * CLK
2 * CLK
0
1
0
8 * CLK
2 * CLK
4 * CLK
0
1
0
1
8 * CLK
2 * CLK
4 * CLK
2 * CLK
0
1
0
8 * CLK
2 * CLK
4 * CLK
0
1
8 * CLK
2 * CLK
1
0
4 * CLK
1
0
1
4 * CLK
2 * CLK
1
0
1
0
4 * CLK
2 * CLK
4 * CLK
1
0
1
4 * CLK
2 * CLK
1
0
4 * CLK
2 * CLK
4 * CLK
1
0
1
4 * CLK
2 * CLK
4 * CLK
2 * CLK
1
0
4 * CLK
2 * CLK
4 * CLK
1
4 * CLK
2 * CLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9350ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9350D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350FA | 功能描述:时钟驱动器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC9350FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC9351 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Low Voltage PLL Clock Driver |
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