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参数资料
型号： MPC932PFA
厂商： MOTOROLA INC
元件分类： 时钟及定时
英文描述： PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装： TQFP-32
文件页数： 4/8页
文件大小： 115K
代理商： MPC932PFA
MPC932P
MOTOROLA
TIMING SOLUTIONS
BR1333 — REV 5
4
Qn Outputs @ 100 MHz, QFB Outputs @ 66 MHz
MPC932P AC CHARACTERISTICS (TA = 0 to 70°C, VCCI = VCCA = VCCO = 3.3 ±5%, VCC_CPU = 2.5 ±5%, 1.8 ±100mV)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tos
Output-to-Output Skew
200
350
ps
Note 4.
tpd
Reference to EXT_FB Average Delay
TCLK
–150
0
150
ps
fref = 50MHz; Note 6.
tpw
Output Duty Cycle (Note 4.)
Q1:5, QFB
Q_CPU @ 2.5V
Q_CPU @ 1.8V
tCYCLE/2
–350
tCYCLE/2
–500
tCYCLE/2
–800
tCYCLE/2
±200
tCYCLE/2
+150
tCYCLE/2
–375
tCYCLE/2
+350
tCYCLE/2
+500
tCYCLE/2
+50
ps
50
W to VCCO/2.
50
W to VCC_CPU/2.
50
W to VCC_CPU/2.
tr, tf
Output Rise/Fall Time (Note 4.)
Q1:5, QFB
Q_CPU @ 2.5V
Q_CPU @ 1.8V
0.1
1.0
2.5
ns
50
W to VCCO/2.
Measured @
0.8V, 2.0V.
50
W to VCC_CPU/2.
Measured @
0.8V, 1.8V.
50
W to VCC_CPU/2.
Measured @
0.4V, 1.4V.
tPLZ, tPHZ
Output Disable Time
2.0
8.0
ns
50
to VCC/2.
tPZL
Output Enable Time
2.0
10
ns
50
to VCC/2.
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
±100
ps
Note 5.
tlock
Maximum PLL Lock Time
10
ms
Qn Outputs @ 66 MHz, QFB Outputs @ 33 MHz
MPC932P AC CHARACTERISTICS (TA = 0 to 70°C, VCCI = VCCA = VCCO = 3.3 ±5%, VCC_CPU = 2.5 ±5%, 1.8 ±100mV)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tos
Output-to-Output Skew
175
350
ps
Note 4.
tpd
Reference to EXT_FB Average Delay
TCLK
–150
0
150
ps
fref = 50MHz; Note 6.
tpw
Output Duty Cycle (Note 4.)
Q1:5, QFB
Q_CPU @ 2.5V
Q_CPU @ 1.8V
tCYCLE/2
–350
tCYCLE/2
–500
tCYCLE/2
–500
tCYCLE/2
±100
tCYCLE/2
±200
tCYCLE/2
±300
tCYCLE/2
+350
tCYCLE/2
+500
tCYCLE/2
+500
ps
50
W to VCCO/2.
50
W to VCC_CPU/2.
50
W to VCC_CPU/2.
tr, tf
Output Rise/Fall Time (Note 4.) Q_CPU, QFB
Q_CPU @ 2.5V
Q_CPU @ 1.8V
0.1
1.0
2.5
ns
50
W to VCCO/2.
Measured @
0.8V, 2.0V.
50
W to VCC_CPU/2.
Measured @
0.8V, 1.8V.
50
W to VCC_CPU/2.
Measured @
0.4V, 1.4V.
tPLZ, tPHZ
Output Disable Time
2.0
8.0
ns
50
to VCC/2.
tPZL
Output Enable Time
2.0
10
ns
50
to VCC/2.
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
±100
ps
Note 5.
tlock
Maximum PLL Lock Time
10
ms
4. Measured with 50
to VCC/2 termination.
5. See Applications Info section for more jitter information.
6. tpd measurement uses the averaging feature of the oscilloscope to remove the jitter component.
相关PDF资料
PDF描述
MPC9331FA PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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MPC9352AC 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9352ACR2 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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