参数资料
型号: MPC932PFA
厂商: MOTOROLA INC
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: TQFP-32
文件页数: 5/8页
文件大小: 115K
代理商: MPC932PFA
MPC932P
TIMING SOLUTIONS
BR1333 — REV 5
5
MOTOROLA
APPLICATIONS INFORMATION
MPC932P
Figure 2. MPC932P Potential Configurations
(Mode = 1)
FBSEL0
‘0’
FBSEL1
‘0’
FB_In
66MHz
Qn
66MHz
QFB
6
1
Input Ref
66MHz
MPC932P
FBSEL0
‘1’
FBSEL1
‘0’
FB_In
83MHz
Qn
66MHz
QFB
6
1
Input Ref
66MHz
MPC932P
FBSEL0
‘1’
FBSEL1
‘0’
FB_In
75MHz
Qn
60MHz
QFB
6
1
Input Ref
60MHz
MPC932P
FBSEL0
‘0’
FBSEL1
‘1’
FB_In
100MHz
Qn
66MHz
QFB
6
1
Input Ref
66MHz
Power Supply Filtering
The MPC932P is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC932P provides separate
power supplies for the output buffers (VCCO) and the internal
PLL (VCCA) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC932P.
Figure 3. Power Supply Filter
VCCA
VCC
MPC932P
0.01
F
22
F
0.01
F
3.3V
RS=10–15
Figure 3 illustrates a typical power supply filter scheme.
The MPC932P is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC932P. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 3 must have a resistance of 10–15
to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor its overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
Although the MPC932P has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
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