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| 型号： | MPC9331AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN 1:6 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:6 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9331 REVISION 7 JANUARY 31, 2013
6
2012 Integrated Device Technology, Inc.
MPC9331 Data Sheet
3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR
Table 7. Characteristics (VCC = 3.3V 5%, TA = 0°C to 70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input reference frequency
2 feedback
PLL mode, external feedback
4 feedback
6 feedback
8 feedback
12 feedback
PLL mode, internal feedback
(
8 feedback)
Input reference frequency in PLL bypass mode(2)
2. In bypass mode, the MPC9331 divides the input reference clock.
100.0
50.0
33.3
25.0
16.67
25.0
240.0
120.0
80.0
60.0
40.0
60.0
240
MHz
PLL locked
fVCO
VCO lock frequency range(3)
3. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO FB.
200
480
MHz
fMAX
Output Frequency
2 output
4 output
6 output
8 output
12 output
100.0
50.0
33.3
25.0
16.67
240.0
120.0
80.0
60.0
40.0
MHz
PLL locked
VPP
Peak-to-peak input voltage
PCLK, PCLK
400
1000
mV
LVPECL
VCMR(4)
4. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Common Mode Range
PCLK, PCLK
1.2
VCC – 0.9
V
LVPECL
tPW,MIN
Input Reference Pulse Width(5)
5. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF,MIN.
2.0
ns
tR, tF
CCLK Input Rise/Fall Time(6)
6. The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), tPW,MIN, DC and fMAX can only
be guaranteed if tR, tF are within the specified range.
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay
CCLK to FB_IN(7)
(static phase offset)
PCLK to FB_IN(7)
CCLK or PCLK to FB_IN(8)
7. Data valid for fREF = 50 MHz and a PLL feedback of 8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1).
8. Data valid for 16.67 MHz < fREF < 100 MHz and any feedback divider. tsk(O) [s] = tsk(O) [] (fREF 360).
–250
–180
–3.0
–130
–30
–50
+120
+3.0
ps
°
FB_SEL = 1 and
PLL locked
tsk(O)
Output-to-output Skew
150
ps
DC
Output duty cycle(9)
9. Output duty cycle is DC = (0.5
500 ps fOUT) 100%. (e.g. the DC range at fOUT = 100 MHz is 45% < DC < 55%).
(T
2)–500
T
2
(T
2)+500
ps
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
8.0
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter(10)
10. All outputs in
4 divider configuration.
200
ps
tJIT(PER)
Period Jitter
125
ps
tJIT()
I/O Phase Jitter
RMS (1
)
25
ps
BW
PLL closed loop bandwidth(11)
4 feedback
PLL mode, external feedback
6 feedback
8 feedback
12 feedback
11. –3 dB point of PLL transfer characteristics.
2.0–8.0
1.2–4.0
1.0–3.0
0.7–2.0
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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