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| 型号： | MPC9351FA |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 13/14页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK DRIVER LV 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:9 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9351 REVISION 6 JANUARY 31, 2013
8
2013 Integrated Device Technology, Inc.
MPC9351 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Calculation of Part-to-Part Skew
The MPC9351 zero-delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9351 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 4. MPC9351 Maximum Device-to-Device Skew
Due to the statistical nature of I/O jitter, a RMS value (1
)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 10.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% (
3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –251 ps to 351 ps relative to TCLK (VCC = 3.3 V and
fVCO = 400 MHz):
tSK(PP)=[–50 ps...150 ps] + [–150 ps...150 ps] +
[(17ps –3)...(17ps 3)] + tPD, LINE(FB)
tSK(PP)=[–251 ps...351 ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for VCC = 3.3 V (17 ps
RMS). I/O jitter is frequency dependant with a maximum at
the lowest VCO frequency (200 MHz for the MPC9351).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
a smaller I/O jitter number at the specific VCO frequency,
resulting in tighter timing limits in zero-delay mode and for
part-to-part skew (tSK(PP)).
Figure 5. Maximum I/O Jitter (RMS)
versus Frequency for VCC = 2.5 V
Figure 6. Maximum I/O Jitter (RMS)
versus Frequency for VCC = 3.3 V
Power Supply Filtering
The MPC9351 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Noise on the
VCCA (PLL) power supply impacts the device characteristics,
for instance, I/O jitter. The MPC9351 provides separate
power supplies for the output buffers (VCC) and the
phase-locked loop (VCCA) of the device. The purpose of this
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment, where it
is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC9351. Figure 7 illustrates a typical power
supply filter scheme. The MPC9351 frequency and phase
stability is most susceptible to noise with spectral content in
Table 10. Confidence Factor CF
CF
Probability of Clock Edge within the Distribution
1
0.68268948
2
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
TCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
30
25
20
15
10
5
0
75
225
250
275
300
325
VCO Frequency [MHz]
t JIT(
)
[ps]
ms
Max. I/O Jitter versus Frequency
350
375
400
30
25
20
15
10
5
0
75
225
250
275
300
325
VCO Frequency [MHz]
t JI
T(
)
[ps]
ms
Max. I/O Jitter versus Frequency
350
375
400
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9351FAR2 | 功能描述:IC PLL CLOCK DRIVER LV 32-LQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| MPC9352 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR |
| MPC9352AC | 功能描述:锁相环 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9352ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-11 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9352FA | 功能描述:锁相环 - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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