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参数资料
| 型号： | MPC941AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 1:27 48-LQFP |
| 标准包装： | 250 |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:27 |
| 差分 - 输入:输出： | 是/无 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 频率 - 最大： | 250MHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
MPC941 REVISION 9 JANUARY 7, 2013
4
2013 Integrated Device Technology, Inc.
MPC941 Data Sheet
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
Table 4. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40 to +85C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fMAX
Maximum Output Frequency
0
250(2)
2. AC characteristics are guaranteed up to fmax. Please refer to applications section for information on power consumption versus operating
frequency and thermal management.
MHz
tr, tf
LVCMOS_CLK Input Rise/Fall Time
1.0(3)
3. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application,
signal transition times smaller than 3 ns can be applied to the MPC941.
ns
0.8 to 2.0 V
tPLH
tPHL
Propagation Delay
PECL_CLK to any Q
LVCMOS_CLK to any Q
1.2
0.9
1.8
1.5
2.6
2.3
ns
tPLZ, HZ
Output Disable Time
ns
tPZL, LZ
Output Enable Time
ns
tsk(O)
Output-to-Output Skew
PECL_CLK to any Q
LVCMOS_CLK to any Q
125
250
ps
tsk(PP)
Device-to-Device Skew
PECL_CLK to any Q
LVCMOS_CLK to any Q
1000
ps
For a given TA and
VCC, any Q
tsk(PP)
Device-to-Device Skew
PECL_CLK to any Q
LVCMOS_CLK to any Q
1400
ps
For any TA, VCC
and Q
DCQ
Output Duty Cycle
PECL_CLK to any Q
LVCMOS_CLK to any Q
45
50
60
55
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
0.2
1.0
ns
0.55 to 2.4 V
Table 5. DC Characteristics (VCC = 2.5 V ± 5%, TA = –40 to +85C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
LVCMOS_CLK
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
LVCMOS_CLK
–0.3
0.7
V
LVCMOS
IIN
Input Current
120(1)
1. Input pull-up / pull-down resistors influence input current.
A
VPP
Peak-to-Peak Input Voltage
PECL_CLK,
PECL_CLK
500
mV
LVPECL
VCMR
Common Mode Range
PECL_CLK,
PECL_CLK
1.1
VCC – 0.7
V
LVPECL
VOH
Output High Voltage
1.8
V
IOH = –15 mA(2)
2. The MPC941 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
VOL
Output Low Voltage
0.6
V
IOL = 15 mA(2)
IOZ
Output Tristate Leakage Current
100
A
ZOUT
Output Impedance
18 – 20
CPD
Power Dissipation Capacitance
7 – 8
10
pF
Per Output
CIN
Input Capacitance
4.0
pF
ICCQ
Maximum Quiescent Supply Current
5
mA
All VCC Pins
VTT
Output Termination Voltage
VCC 2
V
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