- 您现在的位置：买卖IC网 > PDF目录2099 > MPC9443FAR2 (IDT, Integrated Device Technology Inc)IC CLK BUFF DVDR MUX 3:16 48LQFP PDF资料下载
参数资料
| 型号： | MPC9443FAR2 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF DVDR MUX 3:16 48LQFP |
| 标准包装： | 2,000 |
| 类型： | 扇出缓冲器（分配），除法器，多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:16 |
| 差分 - 输入:输出： | 是/无 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 频率 - 最大： | 350MHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 带卷 (TR) |
MPC9443 REVISION 6 AUGUST 23, 2013
5
2013 Integrated Device Technology, Inc.
MPC9443 Data Sheet
2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
Table 7. DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3 V ± 5%, TA = –40 to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
–0.3
0.8
V
LVCMOS
VPP
Peak-to-Peak Input Voltage
PCLK0, 1
250
mV
LVPECL
VCMR(1)
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (DC) specification.
Common Mode Range
PCLK0, 1
1.1
VCC – 0.6
V
LVPECL
IIN
Input Current(2)
2. Input pull-up / pull-down resistors influence input current.
200
A
VIN = GND or VIN = VCC
VOH
Output High Voltage
2.4
V
IOH = –24 mA(3)
3. The MPC9443 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines
(for VCC = 3.3 V) or one 50 series terminated transmission line (for VCC = 2.5 V).
VOL
Output Low Voltage
0.55
0.30
V
IOL = 24 mA(3)
IOL = 12 mA
ZOUT
Output Impedance
19
ICCQ(4)
4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Maximum Quiescent Supply Current
3.0
mA
All VCC Pins
Table 8. AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3 V ± 5%, TA = –40 to +85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
350
MHz
fMAX
Maximum Output Frequency
1 output
2 output
0
350
175
MHz
FSELx = 0
FSELx = 1
VPP
Peak-to-Peak Input Voltage
PCLK0,1
500
1000
mV
LVPECL
VCMR(2)
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (AC) specification.
Common Mode Range
PCLK0,1
1.3
VCC – 0.8
V
LVPECL
tP, REF
Reference Input Pulse Width
1.4
ns
tr, tf
CCLK Input Rise/Fall Time
1.0(3)
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
ns
0.8 to 2.0 V
tPLH
tPHL
tPLH
tPHL
Propagation Delay
PCLK0,1 to any Q
CCLK to any Q
2.5
2.4
2.1
1.9
5.0
5.2
4.2
4.6
ns
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tS, tH
Setup, Hold Time (reference clock to CLK_STOP)
500
ps
tsk(LH, HL) Output-to-Output Skew(4)
Within one bank
Any output, same output divider
Any output, any output divider
4. tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.
125
225
250
ps
tsk(PP)
Device-to-Device Skew (LH)(5)
Using PCLK0,1
Using CCLK
Device-to-Device Skew (LH, HL)(6) Using PCLK0,1
Using CCLK
5. Device-to-device skew referenced to the rising output edge.
6. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge.
2.5
2.1
2.8
2.7
ns
tSK(P)
DCQ
Output Pulse Skew(7)
Using PCLK0,1
Using CCLK
Output Duty Cycle
fQ<140 MHz and using CCLK
fQ<250 MHz and using PCLK0,1
7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |
45
50
300
400
55
ps
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
相关PDF资料 |
PDF描述 |
|---|---|
| MPC9446FAR2 | IC CLK BUFF DVDR MUX 2:10 32LQFP |
| MPC9447ACR2 | IC CLOCK BUFFER MUX 2:9 32-LQFP |
| MPC9448ACR2 | IC CLOCK BUFFER MUX 1:12 32-LQFP |
| MPC9449AER2 | IC CLK BUFF DVDR MUX 3:15 52LQFP |
| MPC94551EFR2 | IC CLOCK BUFFER 1:4 160MHZ 8SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9446 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:2.5V and 3.3V LVCMOS Clock Fanout Buffer |
| MPC9446AC | 功能描述:时钟缓冲器 2.5 3.3V 275MHz Clock Generator RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9446ACR2 | 功能描述:时钟驱动器及分配 FSL 1-10 LVCMOS Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC9446FA | 功能描述:时钟缓冲器 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9446FAR2 | 功能描述:时钟驱动器及分配 FSL 1-10 LVCMOS Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。