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参数资料
| 型号： | MPC9443FAR2 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/15页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF DVDR MUX 3:16 48LQFP |
| 标准包装： | 2,000 |
| 类型： | 扇出缓冲器（分配），除法器，多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:16 |
| 差分 - 输入:输出： | 是/无 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 频率 - 最大： | 350MHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 带卷 (TR) |
MPC9443 REVISION 6 AUGUST 23, 2013
8
2013 Integrated Device Technology, Inc.
MPC9443 Data Sheet
2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC9443 clock driver was designed to drive high-speed
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user, the output drivers were
designed to exhibit the lowest impedance possible. With an output
impedance of less than 20
the drivers can drive either parallel
or series terminated transmission lines at VCC = 3.3 V. For more
information on transmission lines, the reader is referred to
Freescale application note AN1091. In most high performance
clock networks, point-to-point distribution of signals is the method
of choice. In a point-to-point scheme, either series terminated or
parallel terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50
resistance to VCC2.
This technique draws a fairly high level of DC current ,and thus,
only a single terminated line can be driven by each output of the
MPC9443 clock driver. For the series terminated case, however,
there is no DC current draw; thus, the outputs can drive multiple
series terminated lines. Figure 3 illustrates an output driving a
single series terminated line versus two series terminated lines in
parallel. When taken to its extreme, the fanout of the MPC9443
clock driver is effectively doubled due to its capability to drive
multiple lines (at VCC = 3.3 V).
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4 show the simulation results of
an output driving a single line versus two lines. In both cases, the
drive capability of the MPC9443 output buffer is more than
sufficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations, a delta of
only 43 ps exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the MPC9443. The
output waveform in Figure 4 shows a step in the waveform. This
step is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 31
series resistor, plus
the output impedance, does not match the parallel combination of
the line impedances. The voltage wave launched down the two
lines will equal:
VL =VS (Z0 (RS + R0 + Z0))
Z0 =50 || 50
RS =31 || 31
R0 = 19
VL = 3.0 (25 (15.5 + 19 + 25)
=1.26 V
At the load end, the voltage will double, due to the near unity
reflection coefficient, to 2.52 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
Figure 4. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the situation in
Figure 5 should be used. In this case, the series terminating
resistors are reduced such that when the parallel combination is
added to the output buffer impedance, the line impedance is
perfectly matched.
Figure 5. Optimized Dual Line Termination
19
IN
MPC9443
Output
Buffer
RS = 31
ZO = 50
OutA
19
IN
MPC9443
Output
Buffer
RS = 31
ZO = 50
OutB0
RS = 31
ZO = 50
OutB1
Time (ns)
Volt
age
(V
)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
19
MPC9443
Output
Buffer
RS = 12
ZO = 50
RS = 12
ZO = 50
19
+ 12 || 12 = 50 || 50
25
= 25
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9446 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:2.5V and 3.3V LVCMOS Clock Fanout Buffer |
| MPC9446AC | 功能描述:时钟缓冲器 2.5 3.3V 275MHz Clock Generator RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9446ACR2 | 功能描述:时钟驱动器及分配 FSL 1-10 LVCMOS Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC9446FA | 功能描述:时钟缓冲器 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9446FAR2 | 功能描述:时钟驱动器及分配 FSL 1-10 LVCMOS Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
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