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参数资料
| 型号： | MPC9653AAC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:8 3.3V 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:8 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
DATASHEET
3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
NRND
MPC9653A REVISION 4 JANUARY 8, 2013
1
2013 Integrated Device Technology, Inc.
The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and
zero-delay buffer targeted for high performance low-skew clock distribution in
mid-range to high-performance telecom, networking and computing applications.
With output frequencies up to 125 MHz and output skews less than 150 ps the
device meets the needs of the most demanding clock applications.
Features
1:8 PLL based low-voltage clock generator
Supports zero-delay operation
3.3 V power supply
Generates clock signals up to 125 MHz
PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz
Maximum output skew of 150 ps
Differential LVPECL reference clock input
External PLL feedback
Drives up to 16 clock lines
32-lead LQFP packaging
32-lead Pb-free Package Available
Ambient temperature range 0
C to +70C
Pin and function compatible to the MPC953 and MPC9653
NRND – Not Recommend for New Designs
The MPC9653A utilizes PLL technology to frequency lock its outputs onto an
input reference clock. Normal operation of the MPC9653A requires the connec-
tion of the QFB output to the feedback input to close the PLL feedback path (ex-
ternal feedback). With the PLL locked, the output frequency is equal to the
reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5 MHz or 50 to 125 MHz. The
two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine
the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running
at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high
frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25 MHz.
The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use
as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.
The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se-
lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by-
pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes
the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close
the phase locked loop, enabling the PLL to recover to normal operation.
The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission
lines. For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an
effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC9653A
LOW VOLTAGE
3.3 V LVCMOS 1:8
PLL CLOCK GENERATOR
NRND – Not Recommend for New Designs
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9653AAC/W | 功能描述:IC PLL CLK GEN 1:8 3.3V 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| MPC9653AACR2 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9653AACR2/W | 功能描述:IC PLL CLK GEN 1:8 3.3V 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| MPC9653AC | 功能描述:时钟发生器及支持产品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9653AFA | 功能描述:时钟发生器及支持产品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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