参数资料
型号: MPC9653AAC
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/12页
文件大小: 0K
描述: IC PLL CLK GEN 1:8 3.3V 32-LQFP
标准包装: 250
类型: PLL 时钟发生器
PLL: 带旁路
输入: LVCMOS,LVPECL
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 1:8
差分 - 输入:输出: 是/无
频率 - 最大: 125MHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-TQFP(7x7)
包装: 托盘
MPC9653A REVISION 4 JANUARY 8, 2013
8
2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
Figure 6. Single versus Dual Transmission Lines
The waveform plots in Figure 7 show the simulation
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9653A output
buffer is more than sufficient to drive 50
transmission lines
on the incident edge. Note from the delay measurements in
the simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9653A. The output
waveform in Figure 7 shows a step in the waveform, this step
is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36
series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL =VS (Z0 (RS + R0 + Z0))
Z0 =50 || 50
RS =36 || 36
R0 =14
VL = 3.0 (25 (18 + 14 + 25)
=1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 7. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 8, should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 8. Optimized Dual Line Termination
Figure 9. MPC9653A AC Test Reference
14
In
MPC9653A
Output
Buffer
RS = 36
ZO = 50
OutA
14
In
MPC9653A
Output
Buffer
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
Time (ns)
Volt
age
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
14
MPC9653A
Output
Buffer
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 || 22 = 50 || 50
25
= 25
Differential
Pulse Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9653A DUT
VTT
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MPC9653AAC/W 功能描述:IC PLL CLK GEN 1:8 3.3V 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS,LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP(7x7) 包装:带卷 (TR)
MPC9653AACR2 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
MPC9653AACR2/W 功能描述:IC PLL CLK GEN 1:8 3.3V 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS,LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP(7x7) 包装:带卷 (TR)
MPC9653AC 功能描述:时钟发生器及支持产品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
MPC9653AFA 功能描述:时钟发生器及支持产品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56