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参数资料
| 型号： | MPC9653FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, LQFP-32 |
| 文件页数： | 5/9页 |
| 文件大小： | 154K |
| 代理商： | MPC9653FA |
5
MPC9653
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
513
Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input reference frequency
÷4 feedbackb
PLL mode, external feedback
÷8 feedbackc
Input reference frequency in PLL bypass moded
50
25
0
125
62.5
200
MHz
PLL locked
fVCO
VCO lock frequency rangee
200
500
MHz
fMAX
Output Frequency
÷4 feedbackb
÷8 feedbackc
50
25
125
62.5
MHz
PLL locked
VPP
Peak-to-peak input voltage
PCLK
450
1000
mV
LVPECL
VCMRf
Common Mode Range
PCLK
1.2
VCC-0.75
V
LVPECL
tPW,MIN
Input Reference Pulse Widthg
2
ns
t()
Propagation Delay (static phase offset)h
PCLK to FB_IN
–75
125
ps
PLL locked
tPD
Propagation Delay
PLL and divider bypass (BYPASS=0), PCLK to Q0-7
PLL disable (BYPASS=1 and PLL_EN=0), PCLK to Q0-7
1.2
3.0
3.3
7.0
ns
tsk(O)
Output-to-output Skewi
150
ps
tsk(PP)
Device-to-device Skew in PLL and divider bypassj
1.5
ns
BYPASS=0
DC
Output duty cycle
45
50
55
%
PLL locked
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ
Output Disable Time
7.0
ns
tPZL, LZ
Output Enable Time
6.0
ns
tJIT(CC)
Cycle-to-cycle jitter
100
ps
tJIT(PER)
Period Jitter
100
ps
tJIT()
I/O Phase Jitterk
RMS (1
σ)
25
ps
BW
PLL closed loop bandwidthl
÷ 4 feedbackb
PLL mode, external feedback
÷ 8 feedbackc
0.8 – 4
0.5 – 1.3
MHz
tLOCK
Maximum PLL Lock Time
10
ms
a
AC characteristics apply for parallel output termination of 50
to VTT.
b
÷4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
c
÷8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
d
In bypass mode, the MPC9653 divides the input reference clock.
e
The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
fVCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
g
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF,MIN.
E.g. at fREF=100 MHz the input duty cycle range is 20% < DC < 80%.
h
Valid for fREF=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t() [ps] = 50 ps ± (1÷(120 fREF)).
i
See application section for part-to-part skew calculation in PLL zero-delay mode.
j
For a specified temperature and voltage, includes output skew.
k
I/O phase jitter is reference frequency dependent. See application section for details.
l
-3 dB point of PLL transfer characteristics.
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