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参数资料
| 型号： | MPC9653FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, LQFP-32 |
| 文件页数： | 6/9页 |
| 文件大小： | 154K |
| 代理商： | MPC9653FA |
5
MPC9653
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
514
APPLICATIONS INFORMATION
Programming the MPC9653
The MPC9653 supports output clock frequencies from 25 to
125 MHz. Two different feedback divider configurations can be
used to achieve the desired frequency operation range. The
feedback divider (VCO_SEL) should be used to situate the
VCO in the frequency lock range between 200 and 500 MHz
for stable and optimal operation. Two operating frequency
ranges are supported: 25 to 62.5 MHz and 50 to 125 MHz.
Table 9 illustrates the configurations supported by the
MPC9653. PLL zero-delay is supported if BYPASS=1,
PLL_EN=1 and the input frequency is within the specified PLL
reference frequency range.
Table 9: MPC9653 Configurations (QFB connected to FB_IN)
BYPAS
PLL_EN
VCO_SE
Operation
Frequency
S
_
L
p
Ratio
Output range (fQ0-7)
VCO
0
X
Test mode: PLL and divider bypass
fQ0-7 = fREF
0-200 MHz
n/a
1
0
Test mode: PLL bypass
fQ0-7 = fREF ÷ 4
0-50 MHz
n/a
1
0
1
Test mode: PLL bypass
fQ0-7 = fREF ÷ 8
0-25 MHz
n/a
1
0
PLL mode (high frequency range)
fQ0-7 = fREF
50 to 125 MHz
fVCO = fREF 4
1
PLL mode (low frequency range)
fQ0-7 = fREF
25 to 62.5 MHz
fVCO = fREF 8
Power Supply Filtering
The MPC9653 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCCA_PLL power supply impacts the device characteristics,
for instance I/O jitter. The MPC9653 provides separate power
supplies for the output buffers (VCC) and the phase-locked
loop (VCCA_PLL) of the device. The purpose of this design tech-
nique is to isolate the high switching noise digital outputs from
the relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
supply filter on the VCC_PLL pin for the MPC9653. Figure 3
illustrates a typical power supply filter scheme. The MPC9653
frequency and phase stability is most susceptible to noise with
spectral content in the 100kHz to 20MHz range. Therefore the
filter should be designed to target this range. The key parame-
ter that needs to be met in the final filter design is the DC volt-
age drop across the series filter resistor RF. From the data
sheet the ICCA current (the current sourced through the
VCC_PLL pin) is typically 5 mA (10 mA maximum), assuming
that a minimum of 2.985V must be maintained on the VCC_PLL
pin.
Figure 3. VCC_PLL Power Supply Filter
VCC_PLL
VCC
MPC9653
10 nF
RF = 5-15
CF
33...100 nF
RF
VCC
CF = 22 F
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3 “VCC_PLL Power Supply Filter”, the filter
cut-off frequency is around 4 kHz and the noise attenuation at
100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low im-
pedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9653 has several de-
sign features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be ade-
quate to eliminate power supply noise related problems in
most designs.
Using the MPC9653 in zero–delay applications
Nested clock trees are typical applications for the
MPC9653. Designs using the MPC9653 as LVCMOS PLL fan-
out buffer with zero insertion delay will show significantly lower
clock skew than clock distributions developed from CMOS fan-
out buffers. The external feedback option of the MPC9653
clock driver allows for its use as a zero delay buffer. The PLL
aligns the feedback clock output edge with the clock input ref-
erence edge resulting a near zero delay through the device
(the propagation delay through the device is virtually elimi-
nated). The maximum insertion delay of the device in zero-
delay applications is measured between the reference clock
input and any output. This effective delay consists of the static
phase offset, I/O jitter (phase or long-term jitter), feedback path
delay and the output-to-output skew error relative to the feed-
back output.
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