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参数资料
| 型号： | MPC9653FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, LQFP-32 |
| 文件页数： | 8/9页 |
| 文件大小： | 154K |
| 代理商： | MPC9653FA |
5
MPC9653
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
516
put driving a single line versus two lines. In both cases the
drive capability of the MPC9653 output buffer is more than suf-
ficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output-to-output skew of the
MPC9653. The output waveform in Figure 7 “Single versus
Dual Line Termination Waveforms” shows a step in the wave-
form, this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36
se-
ries resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 ( 25 ÷ (18+14+25)
= 1.31V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.6V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
Figure 7. Single versus Dual Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 8 “Optimized Dual Line Termination” should be used.
In this case the series terminating resistors are reduced such
that when the parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
Figure 8. Optimized Dual Line Termination
14
MPC9653
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 k 22 = 50 k 50
25
= 25
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9658 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3V 1:10 LVCMOS PLL Clock Generator |
| MPC9658AC | 功能描述:时钟发生器及支持产品 FSL 1-10 LVCMOS Zero Delay Buffer RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9658ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-10 LVCMOS Zero Delay Buffer RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9658FA | 功能描述:时钟发生器及支持产品 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9658FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9658FAR2 - Tape and Reel |
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