参数资料
型号: MPC9773AE
厂商: IDT, Integrated Device Technology Inc
文件页数: 16/21页
文件大小: 0K
描述: IC PLL CLK GEN 1:12 3.3V 52-LQFP
标准包装: 160
类型: PLL 时钟发生器
PLL: 带旁路
输入: LVCMOS,LVPECL
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 3:12
差分 - 输入:输出: 是/无
频率 - 最大: 242.5MHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 52-LQFP
供应商设备封装: 52-TQFP(10x10)
包装: 托盘
MPC9773 REVISION 6 JANUARY 31, 2013
4
2013 Integrated Device Technology, Inc.
MPC9773 Data Sheet
3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR
MR/OE
1
Outputs disabled (high-impedance state) and device is reset. During reset/
output disable the PLL feedback loop is open and the internal VCO is tied to
its lowest frequency. The MPC9773 requires reset after any loss of PLL lock.
Loss of PLL lock may occur when the external feedback path is interrupted.
The length of the reset pulse should be greater than one reference clock
cycle (CCLKx). The device is reset by the internal power-on reset (POR)
circuitry during power-up.
Outputs enabled (active)
VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency
ratios. See Table 3 to Table 6 and the Applications Section for supported frequency ranges and output to input frequency ratios.
Table 2. Function Table (Configuration Controls)
Control
Default
0
1
Table 3. Output Divider Bank A (NA)
VCO_SEL
FSEL_A1
FSEL_A0
QA[0:3]
0
VCO
8
0
1
VCO
12
0
1
0
VCO
16
0
1
VCO
24
1
0
VCO
4
1
0
1
VCO
6
1
0
VCO
8
1
VCO
12
Table 4. Output Divider Bank B (NB)
VCO_SEL
FSEL_B1
FSEL_B0
QB[0:3]
0
VCO
8
0
1
VCO
12
0
1
0
VCO
16
0
1
VCO
20
1
0
VCO
4
1
0
1
VCO
6
1
0
VCO
8
1
VCO
10
Table 5. Ouput Divider Bank C (NC)
VCO_SEL
FSEL_C1
FSEL_C0
QC[0:3]
0
VCO
4
0
1
VCO
8
0
1
0
VCO
12
0
1
VCO
16
1
0
VCO
2
1
0
1
VCO
4
1
0
VCO
6
1
VCO
8
Table 6. Output Divider PLL Feedback (M)
VCO_SEL
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
0
VCO
8
0
1
VCO
12
0
1
0
VCO
16
0
1
VCO
20
0
1
0
VCO
16
0
1
0
1
VCO
24
0
1
0
VCO
32
0
1
VCO
40
1
0
VCO
4
1
0
1
VCO
6
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