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参数资料
| 型号： | MPC9773AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/21页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
| 标准包装： | 160 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:12 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 242.5MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LQFP |
| 供应商设备封装： | 52-TQFP（10x10） |
| 包装： | 托盘 |
MPC9773 REVISION 6 JANUARY 31, 2013
10
2013 Integrated Device Technology, Inc.
MPC9773 Data Sheet
3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9773 Individual Output Disable (Clock Stop)
Circuitry
The individual clock stop (output enable) control of the
MPC9773 allows designers, under software control, to
implement power management into the clock distribution
design. A simple serial interface and a clock stop control logic
provides a mechanism through which the MPC9773 clock
outputs can be individually stopped in the logic ‘0’ state: The
clock stop mechanism allows serial loading of a 12-bit serial
input register. This register contains one programmable clock
stop bit for 12 of the 14 output clocks. The QC0 and QFB
outputs cannot be stopped (disabled) with the serial port.
The user can program an output clock to stop (disable) by
writing logic ‘0’ to the respective stop enable bit. Likewise, the
user may programmably enable an output clock by writing
logic ‘1’ to the respective enable bit. The clock stop logic
enables or disables clock outputs during the time when the
output would normally be in logic low state, eliminating the
possibility of short or ‘runt’ clock pulses.
The user can write to the serial input register through the
STOP_DATA input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ disable/enable bits. The period of each
STOP_DATA bit equals the period of the free-running
STOP_CLK signal. The STOP_DATA serial transmission
should be timed so the MPC9773 can sample each
STOP_DATA bit with the rising edge of the free-running
STOP_CLK signal. (See Figure 5.)
Figure 5. Clock Stop Circuit Programing
STOP_CLK
STOP_DATA
START
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
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相关代理商/技术参数 |
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| MPC9773AER2 | 功能描述:时钟发生器及支持产品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9773FA | 功能描述:锁相环 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9773FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 52-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9773FAR2 - Tape and Reel |
| MPC9774 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR |
| MPC9774AE | 功能描述:时钟发生器及支持产品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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