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参数资料
| 型号： | MPC998FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 7/7页 |
| 文件大小： | 110K |
| 代理商： | MPC998FAR2 |
4
MPC998
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
443
APPLICATIONS INFORMATION
Power Supply Filtering
The MPC998 is a mixed analog/digital product and as such
it exhibits some sensitivities that would not necessarily be
seen on a fully digital product. Analog circuitry is naturally sus-
ceptible to random noise, especially if this noise is seen on the
power supply pins. The MPC998 provides separate power
supplies for the output buffers (VCCO) and the phase-locked
loop (VCCA) of the device.
The purpose of this design technique is to try and isolate the
high switching noise digital outputs from the relatively sensitive
internal analog phase-locked loop. In a controlled environment
such as an evaluation board this level of isolation is sufficient.
However, in a digital system environment where it is more diffi-
cult to minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC998. Figure
5illustrates a typical power supply filter scheme. The MPC998
is most susceptible to noise with spectral content in the 10kHz
to 1MHz range. Therefore the filter should be designed to tar-
get this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop that will be seen be-
tween the VCC supply and the VCCA pin of the MPC998. From
the data sheet the IVCCA current (the current sourced through
the VCCA pin) is typically 15 mA (20 mA maximum), assuming
that a minimum of 3.3V–5% must be maintained on the VCCA
pin. Very little DC voltage drop can be tolerated when a 3.3V
VCC supply is used. The resistor shown in Figure 5 “Power
Supply Filter” must have a resistance of 5-15
W to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for noise
whose spectral content is above 20 kHz. As the noise frequen-
cy crosses the series resonant point of an individual capacitor
its overall impedance begins to look inductive and thus in-
creases with increasing frequency. The parallel capacitor com-
bination shown ensures that a low impedance path to ground
exists for frequencies well above the bandwidth of the PLL. It is
recommended that the user start with an 8-10
resistor to
avoid potential VCC drop problems and only move to the higher
value resistors when a higher level of attenuation is shown to
be needed.
Figure 5. Power Supply Filter
VCCA
VCC
MPC998
0.01F
22F
0.01F
2.5V or 3.3V
RS=5-15
Although the MPC998 has several design features to mini-
mize the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL) there still may be ap-
plications in which overall performance is being degraded due
to system power supply noise. The power supply filter
schemes discussed in this section should be adequate to elim-
inate power supply noise related problems in most designs.
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相关代理商/技术参数 |
参数描述 |
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| MPC9992 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
| MPC9992AC | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9992ACR2 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9992FA | 功能描述:锁相环 - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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