1
Semiconductor
AC CHARACTERISTICS FOR SYNCHRONOUS READ ( 1/2 )
MR27V3266D
August , 1999
Revision 2.4
32M Synchronous OTP
14
Note
1. Shortage of clock cycles interrupt the data sensing of preceding "Read" command.
The shortage of cycle time for preceding command is detected by internal command controller to cease
the preceding command operation.
The latest "Row Active" or "Read" command is completed.
When legal tCCD is shorter than BL, burst read is terminated with another burst read.
2. Up to 50MHz
Parameter
Symbol
Min
Max
Unit
CLK Cycle time
Data to Valid Output Delay
Data Output Hold Time
CLK High Pulse Width
CLK Low Pulse Width
Input Setup Time
Input Hold Time
CLK to Output in Low-Z
CLK to Output in High-Z
Input Level Transition Time
"Row Active" to "Read" Delay Time
"Read" to "Row Active" delay
( Words of preceding "Read"
command can be read )
< Random Access >
"Read" to "Read" delay
( Words of preceding "Read"
command can be read )
< Sequential Access >
"Row Active" Cycle Time
( Words of preceding "Read"
command can be read )
< Random Access >
"Read" to "Read" delay
( Gapless burst read )
< Sequential Access >
CL = 4
CL = 4
CL = 4
CL = 4
CL = 4
CL = 4
CL = 4
CL = 4
CL = 5
CL = 5
CL = 5
CL = 5
CL = 5
CL = 5
CL = 5
CL = 5
tCRD
tCRD
tCRD
tCRD
tCCD
tCCD
tCCD
tCCD
tRC
tRC
tRC
tRC
tCCD
tCCD
tCCD
tCCD
tCC
tAC
tOH
tCH
tCL
tSI
tHI
tOLZ
tOHZ
tT
tRCD
15
-
3
4
4
3
1.5
0
-
0.1
1CLK
3CLK
3CLK
3CLK
3CLK
3CLK + tRCD
3CLK + tRCD
4CLK
4CLK
4CLK
4CLK
4CLK + tRCD
4CLK + tRCD
4CLK
4CLK
8CLK
8CLK
-
9
-
-
-
-
-
-
10
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Notes
1,2
1
1,2
1
1,2
1
1,2
1
1,2
1
1,2
1
1
BL = 8
BL = 4
BL = 8
BL = 4
BL = 8
BL = 4
BL = 8
BL = 4
"Read" to "Burst Stop" Delay
"Read" to "Precharge" Delay
Power Down Exit Setup Time
tPDE
1CLK
1CLK
tSI + 1CLK
-
-
-
Cycle
Cycle
Cycle
2
2
2CLK
-
Cycle
2