参数资料
型号: MSC1201Y2RHHRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC36
封装: GREEN, PLASTIC, QFN-36
文件页数: 66/93页
文件大小: 1093K
代理商: MSC1201Y2RHHRG4
MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
69
Enable Interrupt Control (EICON)
7
6
5
4
3
2
1
0
Reset Value
SFR D8h
0
1
EAI
AI
WDTI
0
40h
EAI
Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and
bit 5
identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h).
0 = Auxiliary Interrupt disabled (default).
1 = Auxiliary Interrupt enabled.
AI
Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source
bit 4
of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary
Interrupt, if enabled.
0 = No Auxiliary Interrupt detected (default).
1 = Auxiliary Interrupt detected.
WDTI
Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine.
bit 3
Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The
Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in
HCR0.
0 = No Watchdog Timer Interrupt Detected (default).
1 = Watchdog Timer Interrupt Detected.
ADC Results Low Byte (ADRESL)
7
6
5
4
3
2
1
0
Reset Value
SFR D9h
LSB
00h
ADRESL
ADC Results Low Byte. This is the low byte of the ADC results.
bits 70
Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared.
ADC Results Middle Byte (ADRESM)
7
6
5
4
3
2
1
0
Reset Value
SFR DAh
00h
ADRESM
ADC Results Middle Byte. This is the middle byte of the ADC results for the MSC1200/01 and the most significant
byte for the MSC1202.
bits 70
ADC Results High Byte (ADRESH)
7
6
5
4
3
2
1
0
Reset Value
SFR DBh
MSB
00h
ADRESH
ADC Results High Byte. This is the high byte and most significant byte of the ADC results for the MSC1200/01.
bits 70
This is a sign-extended (Bipolar mode) or zero-padded (Unipolar mode) byte for the MSC1202 (that is, all 0s for
positive ADC or unipolar results and all 1s for negative ADC results).
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