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| 型号： | MSC1201Y3RHHRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC36 |
| 封装： | GREEN, PLASTIC, QFN-36 |
| 文件页数： | 23/93页 |
| 文件大小： | 1093K |
| 代理商： | MSC1201Y3RHHRG4 |
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MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
3
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, ADC Bipolar Mode, and
VREF ≡ (REF IN+) (REF IN) = +2.5V, unless otherwise noted.
MSC120x
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Analog Input (AIN0-AIN5, AINCOM)
Analog Input Range
Buffer OFF
AGND 0.1
AVDD + 0.1
V
Analog Input Range
Buffer ON
AGND + 50mV
AVDD 1.5
V
Full-Scale Input Voltage Range
(In+) (In), Bipolar Mode
±VREF/PGA
V
Differential Input Impedance
Buffer OFF
7/PGA(1)
M
Input Current
Buffer ON
0.5
nA
Fast Settling Filter
3dB
0.469
fDATA
Bandwidth
Sinc2 Filter
3dB
0.318
fDATA
Bandwidth
Sinc3 Filter
3dB
0.262
fDATA
Programmable Gain Amplifier
User-Selectable Gain Range
1
128
Input Capacitance
Buffer ON
7
pF
Input Leakage Current
Multiplexer Channel OFF, T = +25
°C
0.5
pA
Burnout Current Sources
Buffer ON
±2
A
ADC Offset DAC
Offset DAC Range
±VREF/(2PGA)
V
Offset DAC Resolution
8
Bits
Offset DAC Full-Scale Gain Error
±1.0
% of Range
Offset DAC Full-Scale Gain Error Drift
0.6
ppm/
°C
System Performance
Resolution
MSC1200, MSC1201
24
Bits
Resolution
MSC1202
16
Bits
ENOB
MSC1200, MSC1201
22
Bits
ENOB
MSC1202
16
Bits
Output Noise
See Typical Characteristics
No Missing Codes
MSC1201, Sinc3 Filter, Decimation > 360
24
Bits
No Missing Codes
MSC1202, Sinc3 Filter
16
Bits
Integral Nonlinearity
End Point Fit, Differential Input
±0.0004
±0.0015
% of FSR
Offset Error
After Calibration
1.5
ppm of FS
Offset Drift(2)
Before Calibration
0.1
ppm of FS/
°C
Gain Error(3)
After Calibration
0.005
%
Gain Error Drift(2)
Before Calibration
0.5
ppm/
°C
System Gain Calibration Range
80
120
% of FS
System Offset Calibration Range
50
% of FS
At DC, VIN = 0V
120
dB
Common-Mode Rejection
fCM = 60Hz, fDATA = 10Hz
130
dB
Common-Mode Rejection
fCM = 50Hz, fDATA = 50Hz
120
dB
fCM = 60Hz, fDATA = 60Hz
120
dB
Normal-Mode Rejection
fCM = 50Hz, fDATA = 50Hz
100
dB
Normal-Mode Rejection
fCM = 60Hz, fDATA = 60Hz
100
dB
Power-Supply Rejection
At DC, dB = 20log(
VOUT/VDD)(4), VIN = 0V
100
dB
(1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7M/64).
(2) Calibration can minimize these errors.
(3) The gain self-calibration cannot have a REF IN+ of more than AVDD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(4) VOUT is change in digital result.
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