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参数资料
| 型号： | MSC1201Y3RHHRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC36 |
| 封装： | GREEN, PLASTIC, QFN-36 |
| 文件页数： | 29/93页 |
| 文件大小： | 1093K |
| 代理商： | MSC1201Y3RHHRG4 |
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MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
35
REGISTER MAP
Figure 21 illustrates the Register Map. It is entirely
separate from the Program and Data Memory areas
discussed previously. A separate class of instructions is
used to access the registers. There are 256 potential
register locations. In practice, the MSC120x have 256
bytes of Scratchpad RAM and up to 128 SFRs. This is
possible since the upper 128 Scratchpad RAM locations
can only be accessed indirectly. Thus, a direct reference
to one of the upper 128 locations must be an SFR access.
Direct RAM is reached at locations 0 to 7Fh (0 to 127).
FFh
255
128
FFh
80h
7Fh
00h
Indirect
RAM
Direct
RAM
Scratchpad
RAM
SFR Registers
Direct
Special Function
Registers
255
128
127
0
Figure 21. Register Map
SFRs are accessed directly between 80h and FFh (128 to
255). The RAM locations between 128 and 255 can be
reached through an indirect reference to those locations.
Scratchpad RAM is available for general-purpose data
storage. Within the 128 bytes of RAM, there are several
special-purpose areas.
Bit Addressable Locations
In addition to direct register access, some individual bits
are also accessible. These are individually addressable
bits in both the RAM and SFR area. In the Scratchpad
RAM area, registers 20h to 2Fh are bit-addressable. This
provides 128 (16
× 8) individual bits available to software.
A bit access is distinguished from a full-register access by
the type of instruction. In the SFR area, any register
location ending in a 0h or 8h is bit-addressable. Figure 22
shows details of the on-chip RAM addressing including the
locations of individual RAM bits.
Working Registers
As part of the lower 128 bytes of RAM, there are four banks
of Working Registers, as shown in Figure 20. The Working
Registers are general-purpose RAM locations that can be
addressed in a special way. They are designated R0
through R7. Since there are four banks, the currently
selected bank will be used by any instruction using R0R7.
This design allows software to change context by simply
switching banks. Bank access is controlled via the
Program Status Word register (PSW; 0D0h) in the SFR
area described below. The 16 bytes immediately above
the R0R7 registers are bit-addressable, so any of the 128
bits in this area can be directly accessed using
bit-addressable instructions.
7Fh
2Fh
7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05
7C
74
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04
7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
2Dh
2Eh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh
18h
17h
10h
0Fh
08h
07h
00h
Direct
RAM
Bank 3
B
it
-A
d
dr
e
s
a
bl
e
Bank 2
Bank 1
Bank 0
MSB
LSB
Figure 22. Scratchpad Register Addressing
Thus, an instruction can designate the value stored in R0
(for example) to address the upper RAM. The 16 bytes
immediately
above
the
these
registers
are
bit-addressable, so any of the 128 bits in this area can be
directly accessed using bit-addressable instructions.
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