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参数资料
| 型号： | MSC1201Y3RHHRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC36 |
| 封装： | GREEN, PLASTIC, QFN-36 |
| 文件页数： | 30/93页 |
| 文件大小： | 1093K |
| 代理商： | MSC1201Y3RHHRG4 |
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MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
36
Stack
Another
use
of
the Scratchpad area is for the
programmer’s stack. This area is selected using the Stack
Pointer (SP, SFR 81h). Whenever a call or interrupt is
invoked, the return address is placed on the Stack. It also
is available to the programmer for variables, etc., since the
Stack can be moved and there is no fixed location within
the RAM designated as Stack. The Stack Pointer defaults
to 07h on reset and the user can then move it as needed.
The SP will point to the last used value. Therefore, the next
value placed on the Stack is put at SP + 1. Each PUSH or
CALL increments the SP by the appropriate value and
each POP or RET decrements it.
Program Memory
After reset, the CPU begins execution from Program
Memory location 0000h. If enabled, the Boot ROM will
appear from address F800h to FFFFh.
Boot ROM
There is a 1kB Boot ROM that controls operation during
serial programming. Additionally, the Boot ROM routines
shown in Table 5 can be accessed during the user mode,
if it is enabled. When enabled, the Boot ROM routines will
be located at memory addresses F800hFBFFh during
user mode.
Table 5. MSC120x Boot ROM Routines
HEX
ADDRESS
ROUTINE
C DECLARATIONS
DESCRIPTION
F802
sfr_rd
char sfr_rd(void);
Return SFR value pointed to by CADDR(1)
F805
sfr_wr
void sfr_wr(char d);
Write to SFR pointed to by CADDR(1)
FBD8
monitor_isr
void monitor_isr() interrupt 6;
Push registers and call cmd_parser
FBDA
cmd_parser
void cmd_parser(void);
See application note SBAA076, Programming the
MSC1210, available at www.ti.com.
FBDC
put_string
void put_string(char code *string);
Output string
FBDE
page_erase
char page_erase(int faddr, char fdata, char fdm);
Erase flash page
FBE0
write_flash
Assembly only; DPTR = address, ACC = data
Flash write(2)
FBE2
write_flash_chk
char write_flash_chk(int faddr, char fdata, char fdm);
Write flash byte, verify
FBE4
write_flash_byte
void write_flash_byte(int faddr, char fdata);
Write flash byte(2)
FBE6
faddr_data_read
char faddr_data_read(char faddr);
Read byte from Configuration Memory
FBE8
data_x_c_read
char data_x_c_read(int faddr, char fdm);
Read xdata or code byte
FBEA
tx_byte
void tx_byte(char);
Send byte to USART0
FBEC
tx_hex
void tx_hex(char);
send hex value to USART0
FBEE
putx
void putx(void);
send “x” to USART0 on R7 = 1
FBF0
rx_byte
char rx_byte(void);
Read byte from USART0
FBF2
rx_byte_echo
char rx_byte_echo(void);
Read and echo byte on USART0
FBF4
rx_hex_echo
char rx_hex_echo(void);
Read and echo hex on USART0
FBF6
rx_hex_dbl_echo
int_rx_hex_dbl_echo(void);
Read int as hex and echo: USART0
FBF8
rx_hex_word_echo
int_rx_hex_word_echo(void);
Read int reversed as hex and echo: USART0
FBFA
autobaud
void autobaud(void);
Set USART0 baud rate after CR(3) received
FBFC
putspace1
void putspace1(void);
Output 1 space to USART0
FBFE
putcr
void putcr(void);
Output CR, LF to USART0
(1) CADDR must be set prior to using these routines.
(2) MWS register (SFR 8Fh) defines Data Memory or Program Memory write.
(3) SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00.
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