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参数资料
| 型号： | MSC7116VF1000 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 49/60页 |
| 文件大小： | 0K |
| 描述： | DSP 16BIT W/DDR CTRLR 400-MAPBGA |
| 标准包装： | 90 |
| 系列： | StarCore |
| 类型： | 定点 |
| 接口： | 主机接口，I²C，UART |
| 时钟速率： | 266MHz |
| 非易失内存： | ROM（8 kB） |
| 芯片上RAM： | 400kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 400-LFBGA |
| 供应商设备封装： | 400-MAPBGA（17x17） |
| 包装： | 托盘 |
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Hardware Design Considerations
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
53
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
8- or 16-bit mode as specified by the H8BIT pin.
Data strobe as specified by the HDSP and HDDS pins.
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note:
When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
3.4.3.2
I2C Boot
When the MSC7116 device is configured to boot from the I
2C port, the boot program configures the GPIO pins for I2C
operation. Then the MSC7116 device initiates accesses to the I
2C module, downloading data to the MSC7116 device. The I2C
interface is configured as follows:
PLL is disabled and bypassed so that the I
2C module is clocked with the IPBus clock.
I
2C interface operates in master mode and polling is used.
EPROM operates in slave mode.
Clock divider is set to 128.
Address of slave during boot is 0xA0.
The IPBus clock is internally divided to generate the bit clock, as follows:
CLKIN must be a maximum of 100 MHz
PLL is bypassed.
IPBus clock = CLKIN/2 is a maximum of 50 MHz.
I2C bit clock must be less than or equal to:
— IPBus clock/I2C clock divider
— 50 MHz (max)/128
— 390.6 KHz
This satisfies the maximum clock rate requirement of 400 kbps for the I2C interface. For details on the boot procedure, see the
“Boot Program” chapter of the MSC711x Reference Manual.
3.4.3.3
SPI Boot
When the MSC7116 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI
operation. Then the MSC7116 device initiates accesses to the SPI module, downloading data to the MSC7116 device. When
the SPI routines run in the boot ROM, the MSC7116 is always configured as the SPI master. Booting through the SPI is
supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory
device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used, at a maximum
frequency of 4 Mbps. Otherwise, the routines for accessing a serial Flash are used, and they can run at faster speeds. Booting is
performed through one of two sets of pins:
Main set: BM[2–3], HA3, and HCS2, which allow use of the PLL.
Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL.
In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot
Program” chapter of the MSC711x Reference Manual.
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| MSC7116VM800 | 功能描述:IC DSP PROCESSOR 16BIT 400MAPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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| MSC7118VF1200 | 功能描述:DSP 16BIT W/DDR CTRLR 400-MAPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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