- 您现在的位置：买卖IC网 > PDF目录80465 > MSM80C85AHGS-2K (LAPIS SEMICONDUCTOR CO LTD) 8-BIT, 5 MHz, MICROPROCESSOR, PQFP44 PDF资料下载
参数资料
| 型号： | MSM80C85AHGS-2K |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROPROCESSOR, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 31/32页 |
| 文件大小： | 355K |
| 代理商： | MSM80C85AHGS-2K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页
7
Semiconductor
MSM80C85AHRS/GS/JS
For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal
interrupt request. The RST 7.5 request flip-flop remains set until the request is serviced. Then
it is reset automatically, This flip-flop may also be reset by using the SIM instruction or by
issuing a
RESET IN to the MSM80C85AH. The RST 7.5 internal flip-flop will be set by a pulse
on the RST 7.5 pin even when the RST 7.5 interrupt is masked out.
The interrupts are arranged in a flixed priority that determines which interrupt is to be
recognized if more than one is pending, as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST
5.5, INTR-lowest priority. This priority scheme does not take into account the priority of a
routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine
if the interrupt are re-enabled before the end of the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic evens such as power failure or bus error. The
TRAP input is recognized just as any other interrupt but has the highest priority. It is not
affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input
must go high and remain high until it is acknowledged. It will not be recognized again until it
goes low, then high again. This avoids any false triggering due to noise or logic glitches. Figure
3 illustrates the TRAP interrupt request circuitry within the MSM80C85AH. Note that the
servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5,INTR) disables all future interrupts
(except TRAPs) until an El instruction is executed.
The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt
enable status. Performing the first RIM instruction following a TRAP interrupt allows you to
determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM
instructions provide current interrupt enable status. Performing a RIM instruction following
INTR or RST 5.5-7.5 will provide current interrupt Enable status, revealing that Interrupts are
disabled.
The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM,
and SIM sets the SOD data.
Inside the MSM80C85AH
External TRAP
Interrupt Request
TRAP
Schmitt
Trigger
RESET IN
RESET
TRAP
Interrupt
Request
+5 V
D
CLK
D
Q
F/F
Clear
TRAP F.F
Internal
TRAP
Acknowledge
Figure 3 Trap and
RESET IN Circuit
相关PDF资料 |
PDF描述 |
|---|---|
| MC9S12HN64VFU | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80 |
| MSP430F2252IRHA | 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQCC40 |
| MK1491-09FTR | 66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| MC68HC705P9MDW | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705P9S | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MSM80C85AHJS | 制造商:ROHM Semiconductor 功能描述: |
| MSM80C85AHRS | 制造商:OK International 功能描述: 制造商:ROHM Semiconductor 功能描述:8bit,CMOS MCU 制造商:ROHM Semiconductor 功能描述:8-bit CMOS microcontroller |
| MSM80C85ARS | 制造商:OK International 功能描述: 制造商:Panasonic Industrial Company 功能描述:IC |
| MSM80C86A-10GS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:16-Bit CMOS MICROPROCESSOR |
| MSM80C86A-10JS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:16-Bit CMOS MICROPROCESSOR |
发布紧急采购，3分钟左右您将得到回复。