参数资料
型号: MSM80C85AHGS-2K
厂商: LAPIS SEMICONDUCTOR CO LTD
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 5 MHz, MICROPROCESSOR, PQFP44
封装: PLASTIC, QFP-44
文件页数: 7/32页
文件大小: 355K
代理商: MSM80C85AHGS-2K
14
Semiconductor
MSM80C85AHRS/GS/JS
AC CHARACTERISTICS
Parameter
Symbol
Condition
Min.
Max.
Unit
CLY Cycle Period
tCYC
tCYC=200 ns
CL=150 pF
200
2000
ns
CLY Low Time
t1
40
ns
CLY High Time
t2
70
ns
CLY Rise and Fall Time
tr, tf
—30
ns
X1 Rising to CLK Rising
tXKR
25
120
ns
X1 Rising to CKK Falling
tXKF
30
150
ns
A8~15 Valid to Leading Edge of Control (1)
tAC
115
ns
AD0~7 Valid to Leading Edge of Control
tACL
115
ns
AD0~15 Valid Data in
tAD
350
ns
Address Float After Leading Edge of RD INTA
tAFR
—0
ns
A8~15 Valid Before Trailing Edge of ALE (1)
tAL
50
ns
AD0~7 Valid Before Trailing Edge of ALE
tALL
50
ns
READY Valid from Address Valid
tARY
100
ns
Address (A8~15) Valid After Control
tCA
60
ns
Width of Control Law (RD, WR, INTA)tCC
230
ns
Trailing Edge of Control to Leading Edges of ALE
tCL
25
ns
Data Valid to Trailing Edge of WR
tDW
230
ns
HLDA to Bus Enable
tHABE
150
ns
Bus Float After HLDA
tHABF
150
ns
HLDA Valid to Trailing Edge of CLK
tHACK
40
ns
HOLD Hold Time
tHDH
0—
ns
HOLD Step Up Time to Trailing Edge of CLK
tHDS
120
ns
INTR Hold Time
tINH
0—
ns
INTR, RST and TRAP Setup Time to Falling Edge of CLK
tINS
150
ns
Address Hold Time After ALE
tLA
50
ns
Trailing Edge of ALE to Leading Edge of Control
tLC
60
ns
ALE Low During CLK High
tLCK
50
ns
ALE to Valid Data During Read
tLDR
270
ns
ALE to Valid Data During Write
tLDW
140
ns
ALE Width
tLL
80
ns
ALE to READY Stable
tLRY
—30
ns
Trailing Edge of RD to Re-enabling of Address
tRAE
90
ns
RD (or INTA) to Valid Data
tRD
150
ns
Control Trailing Edge to Leading Edge of Next Control
tRV
220
ns
Data Hold Time After RD INTA (7)
tRDH
0—
ns
READY Hold Time
tRYH
0—
ns
READY Setup Time to Leading Edge of CLK
tRYS
100
ns
Data Valid After Trailing Edge of WR
tWD
60
ns
LEADING Edge of WR to Data Vaild
tWDL
—20
ns
(Ta = –40°C ~ 85°C, VCC = 4.5 V ~ 5.5 V)
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