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参数资料
| 型号： | MSM82C37B-5VJS |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Programmable DMA Controller(可编程DMA控制器) |
| 中文描述： | 可编程DMA控制器（可编程DMA的控制器） |
| 文件页数： | 16/33页 |
| 文件大小： | 209K |
| 代理商： | MSM82C37B-5VJS |
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16/33
Semiconductor
MSM82C37B-5RS/GS/VJS
DESCRIPTION OF TRANSFER TYPES
MSM82C37B-5 transfers between an I/O and memory devices, or transfers between memory
devices. The three types of transfers between I/O and memory devices are read, write, and
verify.
I/O-Memory Transfers
The operational states during an I/O-memory transfer are S
1
, S
2
, S
3
, and S
4
.
In the S
1
state, an AEN output is changed to high level to indicate that the control signal from
the MSM82C37B-5 is valid. The eight lower order bits of the transfer address are obtained from
A
0
thru A
7
, and the eight higher order bits are obtained from DB
0
thru DB
7
. The ADSTB output
is changed to high level at this time to set the eight higher order bits in an external address latch,
and the DACK output is made active for the channel where the DMA request is acknowledged.
Where there is no change in the eight higher bit transfer address during demand and block mode
transfers, however, the S
1
state is omitted.
In the S
2
state, the
IOR
or
MEMR
output is changed to low level.
In the S
3
state,
IOW
or
MEMW
is changed to low level. Where compressed timing is used,
however, the S
3
state is omitted.
The S
2
and S
3
states are I/O or memory input/output timing control states. In the S
4
state,
IOR
,
IOW
,
MEMR
, and
MEMW
are changed to high level, and the word count register is decremented
by 1 while the address register is incremented (or decremented) by 1. This completes the DMA
transfer of one word.
Note that in I/O-memory transfers, data is transferred directly without being taken in by the
MSM82C37B-5. The differences in the three types of I/O-memory transfers are indicated below.
Read Transfer
Data is transferd from memory to the I/O device by changing
MEMR
and
lOW
to low level.
MEMW
and
IOR
are kept at high level during this time.
Write Transfer
Data is transferred from the I/O device to memory by changing
MEMW
and
IOR
to low level.
MEMR
and
IOW
are kept at high level during this time.
Note that writing and reading in these write and read transfers are with respect to the memory.
Verify Transfer
Although verify transfers involve the same operations as write and read transfers (such as
transfer address generation and
EOP
input responses),they are in fact pseudo transfers where
all I/O and memory reading/writing control signals are kept inactive. READY inputs are
disregarded in verify transfers.
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相关代理商/技术参数 |
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|---|---|
| MSM82C43 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C51A-2GS-K | 制造商:OK International 功能描述:USART, 32 Pin, Plastic, SOP 制造商:OKI Semiconductor 功能描述:USART, 32 Pin, Plastic, SOP |
| MSM82C51A-2JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C51A-2RS | 制造商:ROHM Semiconductor 功能描述: 制造商:ROHM Semiconductor 功能描述:USART,Programmable multifunction 制造商:ROHM Semiconductor 功能描述:USART, programmable multi-function communication interface |
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