参数资料
型号: MSM82C37B-5VJS
厂商: OKI SEMICONDUCTOR CO., LTD.
英文描述: Programmable DMA Controller(可编程DMA控制器)
中文描述: 可编程DMA控制器(可编程DMA的控制器)
文件页数: 18/33页
文件大小: 209K
代理商: MSM82C37B-5VJS
18/33
Semiconductor
MSM82C37B-5RS/GS/VJS
DESCRIPTION OF OPERATION MODES
Single Transfer Mode
In single transfer mode, only one word is transferred, and the addresses are incremented (or
decremented) by 1 while the word count is decremented by 1. The HRQ is then changed to low
level to return the bus control to the CPU. If DREQ remains active after completion of a transfer,
the HRQ is changed to low level. After the HLDA is changed to low level by the CPU, and then
changes the HRQ back to high level to commence a fresh DMA cycle. For this reason, a machine
cycle can be inserted between DMA cycles by the CPU.
Block Transfer Mode
Once a DMA transfer is started in block mode, the transfer is continued until terminal count (TC)
status is reached.
If DREQ remains active until DACK becomes active, the DMA transfer is continued even if
DREQ becomes inactive.
Demand Transfer Mode
The DMA transfer is continued in demand transfer mode until DREQ is no longer active, or until
TC status is reached.
During a DMA transfer, intermediate address and word count values are held in the current
address and current word count registers. Consequently, if the DMA transfer is suspended as
a result of DREQ becoming inactive before TC status is reached, and the DREQ for that channel
is then made active again, the suspended DMA transfer is resumed.
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