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参数资料
| 型号： | MSM82C37B-5VJS |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Programmable DMA Controller(可编程DMA控制器) |
| 中文描述： | 可编程DMA控制器（可编程DMA的控制器） |
| 文件页数： | 17/33页 |
| 文件大小： | 209K |
| 代理商： | MSM82C37B-5VJS |
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Semiconductor
MSM82C37B-5RS/GS/VJS
Memory-memory Transfer
Memory-memory transfers are used to transfer data blocks from one memory area to another.
Memory-memory transfers require a total of eight states to complete a single transfer four states
(S
11
thru S
14
) for reading from memory, and four states (S
21
thru S
24
) for writing into memory.
These states are similar to I/O-memory transfer states, and are distinguished by using two-digit
numbers. In memory-memory transfers, channel 0 is used for reading data from the source area,
and channel 1 is used for writing data into the destination area. During the initial four states,
data specified by the channel 0 address is read from the memory when MEMR is made active,
and is taken in the MSM82C37B-5 temporary register. Then during the latter four states, the data
in the temporary register is written in the address specified by channel 1. This completes the
transfer of one byte of data. With channel 0 and channel 1 addresses subsequently incremented
(or decremented) by 1, and channel 0, 1 word count decremented by 1, this operation is repeated.
The transfer is terminated when the word count reaches FFFF(H) from 0000(H), or when an
EOP
input is applied from an external source. Note that there is no DACK output signal during this
transfer.
The following preparations in programming are requiring to enable memory-memory transfers
to be started.
Command Register Setting
Memory-memory transfers are enabled by setting bit 0. Channel 0 address can be held for all
transfers by setting bit 1. This setting can be used to enable 1-word contents of the source area
to be written into the entire destination area.
Mode Register Setting
The transfer type destination is disregarded in channels 0 and 1. Memory-memory transfers are
always executed in block transfer mode.
Request Register Setting
Memory-memory transfers are started by setting the channel 0 request bit.
MASK REGISTER SETTING
Mask bits for all channels are set to prevent selection of any other channel apart from channel
0.
Word Count Register Setting
The channel 1 word count is validated, while the channel 0 word count is disregarded.
In order to autoinitialize both channels, it is necessary to write the same values into both word
count registers.
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相关代理商/技术参数 |
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| MSM82C43 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:INPUT/OUTPUT PORT EXPANDER |
| MSM82C51A-2GS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER |
| MSM82C51A-2GS-K | 制造商:OK International 功能描述:USART, 32 Pin, Plastic, SOP 制造商:OKI Semiconductor 功能描述:USART, 32 Pin, Plastic, SOP |
| MSM82C51A-2JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C51A-2RS | 制造商:ROHM Semiconductor 功能描述: 制造商:ROHM Semiconductor 功能描述:USART,Programmable multifunction 制造商:ROHM Semiconductor 功能描述:USART, programmable multi-function communication interface |
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