参数资料
型号: MSP430F248TRGC
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, QCC64
封装: PLASTIC, QFN-64
文件页数: 50/91页
文件大小: 1246K
代理商: MSP430F248TRGC
MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547H
– JUNE 2007 – REVISED AUGUST 2011
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
fUSCI
USCI input clock frequency
External: UCLK
fSYSTEM
MHz
Duty cycle = 50%
± 10%
BITCLK clock frequency
fBITCLK
2.2 V/3 V
1
MHz
(equals baud rate in MBaud)(1)
2.2 V
50
150
tτ
UART receive deglitch time(2)
ns
3 V
50
100
(1)
The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
(2)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
USCI (SPI Master Mode)
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
SMCLK, ACLK
fUSCI
USCI input clock frequency
fSYSTEM
MHz
Duty cycle = 50%
± 10%
2.2 V
110
tSU,MI
SOMI input data setup time
ns
3 V
75
2.2 V
0
tHD,MI
SOMI input data hold time
ns
3 V
0
2.2 V
30
UCLK edge to SIMO valid,
tVALID,MO
SIMO output data valid time
ns
CL = 20 pF
3 V
20
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave
's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI Slave Mode)
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE low to clock
2.2 V/3 V
50
ns
tSTE,LAG
STE lag time, Last clock to STE high
2.2 V/3 V
10
ns
tSTE,ACC
STE access time, STE low to SOMI data out
2.2 V/3 V
50
ns
STE disable time, STE high to SOMI high
tSTE,DIS
2.2 V/3 V
50
ns
impedance
2.2 V
20
tSU,SI
SIMO input data setup time
ns
3 V
15
2.2 V
10
tHD,SI
SIMO input data hold time
ns
3 V
10
2.2 V
75
110
UCLK edge to SOMI valid,
tVALID,SO
SOMI output data valid time
ns
CL = 20 pF
3 V
50
75
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master
's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
54
Copyright
2007–2011, Texas Instruments Incorporated
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