参数资料
型号: MSP430F5519IPN
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQFP80
封装: GREEN, PLASTIC, LQFP-80
文件页数: 81/119页
文件大小: 1351K
代理商: MSP430F5519IPN
MSP430F551x
MSP430F552x
SLAS590E
– MARCH 2009 – REVISED APRIL 2011
USCI (SPI Master Mode) - recommended operating conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
fUSCI
USCI input clock frequency
fSYSTEM
MHz
Duty cycle = 50%
± 10%
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
SMCLK, ACLK
fUSCI
USCI input clock frequency
fSYSTEM
MHz
Duty cycle = 50%
± 10%
1.8 V
55
PMMCOREV = 0
ns
3.0 V
38
tSU,MI
SOMI input data setup time
2.4 V
30
PMMCOREV = 3
ns
3.0 V
25
1.8 V
0
PMMCOREV = 0
ns
3.0 V
0
tHD,MI
SOMI input data hold time
2.4 V
0
PMMCOREV = 3
ns
3.0 V
0
UCLK edge to SIMO valid,
1.8 V
20
CL = 20 pF
ns
3.0 V
18
PMMCOREV = 0
tVALID,MO
SIMO output data valid time(2)
UCLK edge to SIMO valid,
2.4 V
16
CL = 20 pF
ns
3.0 V
15
PMMCOREV = 3
1.8 V
-10
CL = 20 pF
ns
PMMCOREV = 0
3.0 V
-8
tHD,MO
SIMO output data hold time(3)
2.4 V
-10
CL = 20 pF
ns
PMMCOREV = 3
3.0 V
-8
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave
's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2)
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
(3)
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
64
Copyright
2009–2011, Texas Instruments Incorporated
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