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参数资料
| 型号： | MT24D836M |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 8Meg x 36 Parity DRAM SIMMs(8M x 36奇偶校验动态RAM（单列直插存储器模块）) |
| 中文描述： | 8Meg × 36平价的DRAM的SIMM（8米× 36奇偶校验动态随机存储器（单列直插存储器模块）） |
| 文件页数： | 1/17页 |
| 文件大小： | 308K |
| 代理商： | MT24D836M |
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
1
4, 8 MEG x 36
PARITY DRAM SIMMs
OBSOLETE
DRAM
MODULE
MT12D436
MT24D836
FEATURES
JEDEC- and industry-standard pinout in a 72-pin,
single in-line memory module (SIMM)
16MB (4 Meg x 36) and 32MB (8 Meg x 36) parity
versions
High-performance CMOS silicon-gate process
Single 5V
±
10% power supply
All inputs, outputs and clocks are TTL-compatible
Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
2,048-cycle refresh distributed across 32ms
FAST PAGE MODE (FPM) access cycle
Multiple RAS# lines allow x18 or x36 widths
OPTIONS
Timing
60ns access
Packages
72-pin SIMM
72-pin SIMM (gold)
72-pin SIMM low profile (1.00")
72-pin SIMM (gold) low profile (1.00")
MARKING
-6
M
G
DM
DG
GENERAL DESCRIPTION
The MT12D436 and MT24D836 are randomly accessed
16MB and 32MB solid-state memories organized in a x36
configuration. During READ or WRITE cycles, each bit is
uniquely addressed through the 22 address bits, which are
entered 11 bits (A0-A10) at a time. RAS# is used to latch the
first 11 bits and CAS# the latter 11 bits. A READ or WRITE
KEY TIMING PARAMETERS
SPEED
-6
t
RC
110ns
t
RAC
60ns
t
PC
35ns
t
AA
30ns
t
CAC
15ns
t
RP
40ns
PART NUMBERS
PART NUMBER
MT12D436G-xx
MT12D436M-xx
MT12D436DG-xx
MT12D436DM-xx
MT24D836G-xx
MT24D836M-xx
xx = speed
CONFIGURATION
4 Meg x 36
4 Meg x 36
4 Meg x 36
4 Meg x 36
8 Meg x 36
8 Meg x 36
PLATING
Gold
Tin/Lead
Gold
Tin/Lead
Gold
Tin/Lead
HEIGHT
1.190"
1.190"
1.000"
1.000"
1.190"
1.190"
NOTE:
Symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SYMBOL
Vss
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
DQ4
DQ22
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
PIN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SYMBOL
A10
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
DQ8
DQ26
A7
NC (A11)
Vcc
A8
A9
NC/RAS3#*
RAS2#
DQ27
DQ9
PIN
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
SYMBOL
DQ18
DQ36
Vss
CAS0#
CAS2#
CAS3#
CAS1#
RAS0#
NC/RAS1#*
NC
WE#
NC
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
PIN
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SYMBOL
DQ13
DQ31
DQ14
DQ32
Vcc
DQ33
DQ15
DQ34
DQ16
DQ35
DQ17
NC
PRD1
PRD2
PRD3
PRD4
NC
Vss
*32MB version only
72-Pin SIMM
(DD-5) 4 Meg x 36 (shown)
(DD-6) 8 Meg x 36
(DD-7) 4 Meg x 36 Low Profile
PIN ASSIGNMENT (Front View)
cycle is selected with the WE# input. A logic HIGH on WE#
dictates READ mode, while a logic LOW on WE# dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of CAS#. Since WE# goes LOW prior to
CAS# going LOW, the output pin(s) remain open (High-Z)
until the next CAS# cycle.
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