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参数资料
| 型号： | MT2D18 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 1 Meg x 8 DRAM Module(5V，1M x 8 动态RAM模块) |
| 中文描述： | 1梅格× 8内存模块（5V的，100万× 8动态内存模块） |
| 文件页数： | 1/11页 |
| 文件大小： | 174K |
| 代理商： | MT2D18 |
MT2D18
DM01.pm5 – Rev. 2/95
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1995, Micron Technology, Inc.
1
MT2D18
1 MEG x 8 DRAM MODULE
OBSOLETE
FEATURES
JEDEC- and industry-standard pinout in a 30-pin,
single-in-line memory module (SIMM)
High-performance CMOS silicon-gate process
Single 5V
±
10% power supply
Low power, 6mW standby; 450mW active, typical
All device pins are TTL-compatible
FAST PAGE MODE (FPM) access cycle
Refresh modes:
R
A
/
S ONLY,
C
A
/
S-BEFORE-
R
A
/
S (CBR)
and HIDDEN
Low profile
1,024-cycle refresh distributed across 16ms
OPTIONS
Timing
60ns access
70ns access
MARKING
-6
-7
Packages
30-pin SIMM
M
Part Number Example: MT2D18M-6
DRAM
MODULE
1 MEG x 8
1 MEGABYTE, 5V,
FAST PAGE MODE
PIN ASSIGNMENT (Front View)
30-Pin SIMM
(DD-1)
Vcc
CAS
DQ1
A0
A1
DQ2
A2
A3
Vss
DQ3
A4
A5
DQ4
A6
A7
DQ5
A8
A9
NC
DQ6
WE
Vss
DQ7
NC
DQ8
NC
RAS
NC
NC
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GENERAL DESCRIPTION
The MT2D18 is a randomly accessed solid-state memory
containing 1,048,576 words organized in a x8 configuration.
During READ or WRITE cycles, each word is uniquely
addressed through 20 address bits, which are entered 10
bits (A0-A9) at a time.
R
A
/
S is used to latch the first 10 bits
and
C
A
/
S the latter 10 bits. READ or WRITE cycles are
selected with the
W
/
E input. A logic HIGH on
W
/
E dictates
READ mode while a logic LOW on
W
/
E dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of
W
/
E or
C
A
/
S, whichever occurs last. Early
WRITE occurs when
W
/
E goes LOW prior to
C
A
/
S going
LOW, and the output pins remain open (High-Z) until the
next
C
A
/
S cycle.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
(A0-A9) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by
R
A
/
S
followed by a column-address strobed-in by
C
A
/
S.
C
A
/
S
may be toggled-in by holding
R
A
/
S LOW and strobing-in
different column-addresses, thus executing faster memory
cycles.
KEY TIMING PARAMETERS
SPEED
-6
-7
t
RC
110ns
130ns
t
RAC
60ns
70ns
t
PC
35ns
40ns
t
AA
30ns
35ns
t
CAC
15ns
20ns
t
RP
40ns
50ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT2D25632G-7 | 制造商:Micron Technology Inc 功能描述: |
| MT2DT132G-52B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Burst EDO Page Mode DRAM Module |
| MT2DT132G-60B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Burst EDO Page Mode DRAM Module |
| MT2DT132M-52B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Burst EDO Page Mode DRAM Module |
| MT2DT132M-60B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Burst EDO Page Mode DRAM Module |
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