参数资料
型号: MT2D18
厂商: Micron Technology, Inc.
英文描述: 1 Meg x 8 DRAM Module(5V,1M x 8 动态RAM模块)
中文描述: 1梅格× 8内存模块(5V的,100万× 8动态内存模块)
文件页数: 4/11页
文件大小: 174K
代理商: MT2D18
MT2D18
DM01.pm5 – Rev. 2/95
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1995, Micron Technology, Inc.
4
MT2D18
1 MEG x 8 DRAM MODULE
OBSOLETE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16) (V
CC
= +5V
±
10%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to
R
A
/
S)
Column-address setup time
Row-address setup time
Access time from
C
A
/
S
Column-address hold time
C
A
/
S pulse width
C
A
/
S hold time (CBR REFRESH)
C
A
/
S to output in Low-Z
C
A
/
S precharge time
Access time from
C
A
/
S precharge
C
A
/
S to
R
A
/
S precharge time
C
A
/
S hold time
C
A
/
S setup time (CBR REFRESH)
Write command to
C
A
/
S lead time
Data-in hold time
Data-in hold time (referenced to
R
A
/
S)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from
R
A
/
S
R
A
/
S to column-address delay time
Row-address hold time
Column-address to
R
A
/
S lead time
R
A
/
S pulse width
R
A
/
S pulse width (FAST PAGE MODE)
-6
-7
SYM
t
AA
t
AR
t
ASC
t
ASR
t
CAC
t
CAH
t
CAS
t
CHR
t
CLZ
t
CP
t
CPA
t
CRP
t
CSH
t
CSR
t
CWL
t
DH
t
DHR
t
DS
t
OFF
t
PC
t
PRWC
t
RAC
t
RAD
t
RAH
t
RAL
t
RAS
t
RASP
MIN
MAX
30
MIN
MAX
35
UNITS
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n/a
ns
ns
ns
ns
ns
ns
NOTES
45
0
0
50
0
0
15
20
9
10
15
10
0
10
15
20
10
0
10
10,000
10,000
19
18
35
40
10
60
10
15
10
45
0
3
35
n/a
10
70
10
20
15
55
0
3
40
n/a
19
15
15
15
20
12, 27
21
8
22
60
30
70
35
15
10
30
60
60
15
10
35
70
70
10,000
100,000
10,000
100,000
CAPACITANCE
PARAMETER
Input Capacitance: A0-A9
Input Capacitance:
R
A
/
S,
C
A
/
S,
W
/
E
Input/Output Capacitance: DQ1-DQ8
SYMBOL
C
I
1
C
I
2
C
IO
MIN
MAX
13
17
10
UNITS
pF
pF
pF
NOTES
17
17
17
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