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参数资料
| 型号： | MT2D18 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 1 Meg x 8 DRAM Module(5V，1M x 8 动态RAM模块) |
| 中文描述： | 1梅格× 8内存模块（5V的，100万× 8动态内存模块） |
| 文件页数： | 6/11页 |
| 文件大小： | 174K |
| 代理商： | MT2D18 |
MT2D18
DM01.pm5 – Rev. 2/95
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1995, Micron Technology, Inc.
6
MT2D18
1 MEG x 8 DRAM MODULE
OBSOLETE
NOTES
1. All voltages referenced to V
SS
.
2. I
CC
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
3. An initial pause of 100
μ
s is required after power-up
followed by any eight
R
A
/
S refresh cycles (
R
A
/
S ONLY
or CBR with
W
/
E HIGH) before proper device
operation is assured. The eight
R
A
/
S cycle wake-ups
should be repeated any time the
t
REF refresh
requirement is exceeded.
4. AC characteristics assume
t
T = 5ns.
5. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0
°
C
≤
T
A
≤
70
°
C) is assured.
7. Measured with a load equivalent to two TTL gates
and 100pF.
8. Assumes that
t
RCD <
t
RCD (MAX). If
t
RCD is greater
than the maximum recommended value shown in this
table,
t
RAC will increase by the amount that
t
RCD
exceeds the value shown.
9. Assumes that
t
RCD
≥
t
RCD (MAX).
10. If
C
A
/
S = V
IH
, data output is High-Z.
11. If
C
A
/
S = V
IL
, data output may contain data from the
last valid READ cycle.
12.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
13. Operation within the
t
RCD (MAX) limit ensures that
t
RAC (MAX) can be met.
t
RCD (MAX) is specified as
a reference point only; if
t
RCD is greater than the
specified
t
RCD (MAX) limit, then access time is
controlled exclusively by
t
CAC.
14.
t
RCH is referenced to the first rising edge of
R
A
/
S or
C
A
/
S.
15. These parameters are referenced to
C
A
/
S leading edge
in EARLY WRITE cycles.
16. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
17. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
V
CC
= 5V, DC bias = 2.4V at 15mV RMS).
18. If
C
A
/
S is LOW at the falling edge of
R
A
/
S, data-out
(Q) will be maintained from the previous cycle. To
initiate a new cycle and clear the Q buffer,
C
A
/
S must
be pulsed HIGH for
t
CP.
19. On-chip refresh and address counters are enabled.
20. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case,
W
/
E = LOW.
21. LATE WRITE, READ WRITE or READ-MODIFY-
WRITE cycles are not available due to
O
/
E being
grounded on U1 and U2.
22. Operation within the
t
RAD (MAX) limit ensures that
t
RAC (MIN) and
t
CAC (MIN) can be met.
t
RAD
(MAX) is specified as a reference point only; if
t
RAD
is greater than the specified
t
RAD (MAX) limit, then
access time is controlled exclusively by
t
AA.
23.
t
WTS and
t
WTH are setup and hold specifications for
the
W
/
E pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of
t
WRP and
t
WRH in the
CBR REFRESH cycle.
24. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
25. All other inputs at V
CC
-0.2V.
26. I
CC
is dependent on cycle rates.
27. The 3ns minimum is a parameter guaranteed by
design.
28. Column-address changed once each cycle.
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