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参数资料
| 型号： | MT42L256M32D4KP-3 IT:A |
| 厂商： | Micron Technology Inc |
| 文件页数： | 7/164页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR2 SDRAM 8GBIT 168FBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR2 SDRAM |
| 存储容量： | 8G（356M x 32） |
| 速度： | 333MHz |
| 接口： | 并联 |
| 电源电压： | 1.14 V ~ 1.3 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 168-VFBGA |
| 供应商设备封装： | 168-FBGA（12x12） |
| 包装： | 散装 |
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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Figure 51: READ Burst with Auto Precharge – RL = 3, BL = 4, RU( t RTP(MIN)/ t CK) = 2 ........................................ 72
Figure 52: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 73
Figure 53: Regular Distributed Refresh Pattern ............................................................................................... 77
Figure 54: Supported Transition from Repetitive REFRESH Burst .................................................................... 78
Figure 55: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 79
Figure 56: Recommended Self Refresh Entry and Exit ..................................................................................... 80
Figure 57: t SRF Definition .............................................................................................................................. 81
Figure 58: All-Bank REFRESH Operation ........................................................................................................ 81
Figure 59: Per-Bank REFRESH Operation ....................................................................................................... 82
Figure 60: SELF REFRESH Operation .............................................................................................................. 83
Figure 61: MRR Timing – RL = 3, t MRR = 2 ...................................................................................................... 85
Figure 62: READ to MRR Timing – RL = 3, t MRR = 2 ......................................................................................... 86
Figure 63: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 87
Figure 64: Temperature Sensor Timing ........................................................................................................... 89
Figure 65: MR32 and MR40 DQ Calibration Timing – RL = 3, t MRR = 2 ............................................................. 90
Figure 66: MODE REGISTER WRITE Timing – RL = 3, t MRW = 5 ....................................................................... 91
Figure 67: ZQ Timings ................................................................................................................................... 93
Figure 68: Power-Down Entry and Exit Timing ................................................................................................ 95
Figure 69: CKE Intensive Environment ........................................................................................................... 95
Figure 70: REFRESH-to-REFRESH Timing in CKE Intensive Environments ...................................................... 95
Figure 71: READ to Power-Down Entry ........................................................................................................... 96
Figure 72: READ with Auto Precharge to Power-Down Entry ............................................................................ 97
Figure 73: WRITE to Power-Down Entry ......................................................................................................... 98
Figure 74: WRITE with Auto Precharge to Power-Down Entry .......................................................................... 99
Figure 75: REFRESH Command to Power-Down Entry ................................................................................... 100
Figure 76: ACTIVATE Command to Power-Down Entry .................................................................................. 100
Figure 77: PRECHARGE Command to Power-Down Entry .............................................................................. 100
Figure 78: MRR Command to Power-Down Entry .......................................................................................... 101
Figure 79: MRW Command to Power-Down Entry ......................................................................................... 101
Figure 80: Deep Power-Down Entry and Exit Timing ...................................................................................... 102
Figure 81: Simplified Bus Interface State Diagram .......................................................................................... 104
Figure 82: V REF DC Tolerance and V REF AC Noise Limits ................................................................................. 120
Figure 83: LPDDR2-466 to LPDDR2-1066 Input Signal ................................................................................... 121
Figure 84: LPDDR2-200 to LPDDR2-400 Input Signal ..................................................................................... 122
Figure 85: Differential AC Swing Time and t DVAC .......................................................................................... 123
Figure 86: Single-Ended Requirements for Differential Signals ....................................................................... 125
Figure 87: V IX Definition ............................................................................................................................... 126
Figure 88: Differential Input Slew Rate Definition for CK, CK#, DQS, and DQS# ............................................... 127
Figure 89: Single-Ended Output Slew Rate Definition ..................................................................................... 128
Figure 90: Differential Output Slew Rate Definition ........................................................................................ 129
Figure 91: Overshoot and Undershoot Definition ........................................................................................... 130
Figure 92: HSUL_12 Driver Output Reference Load for Timing and Slew Rate ................................................. 131
Figure 93: Output Driver ............................................................................................................................... 132
Figure 94: Output Impedance = 240 Ohms, I-V Curves After ZQRESET ............................................................ 135
Figure 95: Output Impedance = 240 Ohms, I-V Curves After Calibration ......................................................... 136
Figure 96: Command Input Setup and Hold Timing ....................................................................................... 149
Figure 97: Typical Slew Rate and t VAC – t IS for CA and CS# Relative to Clock ................................................... 152
Figure 98: Typical Slew Rate – t IH for CA and CS# Relative to Clock ................................................................. 153
Figure 99: Tangent Line – t IS for CA and CS# Relative to Clock ........................................................................ 154
Figure 100: Tangent Line – t IH for CA and CS# Relative to Clock ..................................................................... 155
Figure 101: Typical Slew Rate and t VAC – t DS for DQ Relative to Strobe ........................................................... 159
Figure 102: Typical Slew Rate – t DH for DQ Relative to Strobe ......................................................................... 160
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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| MT42L256M32D4KP-MS | 制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk |
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