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参数资料
| 型号： | MT42L256M32D4KP-3 IT:A |
| 厂商： | Micron Technology Inc |
| 文件页数： | 9/164页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR2 SDRAM 8GBIT 168FBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR2 SDRAM |
| 存储容量： | 8G（356M x 32） |
| 速度： | 333MHz |
| 接口： | 并联 |
| 电源电压： | 1.14 V ~ 1.3 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 168-VFBGA |
| 供应商设备封装： | 168-FBGA（12x12） |
| 包装： | 散装 |
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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Single Channel S4 Configuration Addressing ........................................................................................ 2
Table 3: Dual Channel S4 Configuration Addressing .......................................................................................... 2
Table 4: 128 Meg x 16 I DD Specifications ......................................................................................................... 12
Table 5: 64 Meg x 32 I DD Specifications ........................................................................................................... 13
Table 6: I DD6 Partial-Array Self Refresh Current ............................................................................................... 15
Table 7: Ball/Pad Descriptions ....................................................................................................................... 38
Table 8: Initialization Timing Parameters ....................................................................................................... 42
Table 9: Power-Off Timing ............................................................................................................................. 43
Table 10: Mode Register Assignments ............................................................................................................. 44
Table 11: MR0 Device Information (MA[7:0] = 00h) ......................................................................................... 45
Table 12: MR0 Op-Code Bit Definitions .......................................................................................................... 45
Table 13: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 45
Table 14: MR1 Op-Code Bit Definitions .......................................................................................................... 45
Table 15: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) ................................. 46
Table 16: No-Wrap Restrictions ...................................................................................................................... 47
Table 17: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 47
Table 18: MR2 Op-Code Bit Definitions .......................................................................................................... 48
Table 19: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 48
Table 20: MR3 Op-Code Bit Definitions .......................................................................................................... 48
Table 21: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 48
Table 22: MR4 Op-Code Bit Definitions .......................................................................................................... 49
Table 23: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 49
Table 24: MR5 Op-Code Bit Definitions .......................................................................................................... 49
Table 25: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 49
Table 26: MR6 Op-Code Bit Definitions .......................................................................................................... 50
Table 27: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 50
Table 28: MR7 Op-Code Bit Definitions .......................................................................................................... 50
Table 29: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 50
Table 30: MR8 Op-Code Bit Definitions .......................................................................................................... 50
Table 31: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 51
Table 32: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 51
Table 33: MR10 Op-Code Bit Definitions ........................................................................................................ 51
Table 34: MR[11:15] Reserved (MA[7:0] = 0Bh–0Fh) ......................................................................................... 51
Table 35: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 51
Table 36: MR16 Op-Code Bit Definitions ........................................................................................................ 51
Table 37: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 52
Table 38: MR17 PASR Segment Mask Definitions ............................................................................................ 52
Table 39: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 52
Table 40: Reserved Mode Registers ................................................................................................................. 52
Table 41: MR63 RESET (MA[7:0] = 3Fh) – MRW Only ....................................................................................... 53
Table 42: Bank Selection for PRECHARGE by Address Bits ............................................................................... 69
Table 43: PRECHARGE and Auto Precharge Clarification ................................................................................. 73
Table 44: REFRESH Command Scheduling Separation Requirements .............................................................. 75
Table 45: Bank and Segment Masking Example ............................................................................................... 84
Table 46: Temperature Sensor Definitions and Operating Conditions .............................................................. 88
Table 47: Data Calibration Pattern Description ............................................................................................... 90
Table 48: Truth Table for MRR and MRW ........................................................................................................ 91
Table 49: Command Truth Table ................................................................................................................... 105
Table 50: CKE Truth Table ............................................................................................................................. 106
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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