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参数资料
| 型号： | MT46V32M4TG-75 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 26/68页 |
| 文件大小： | 2547K |
| 代理商： | MT46V32M4TG-75 |
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26
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
WRITES
WRITE bursts are initiated with a WRITE com-
mand, as shown in Figure 14.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic WRITE commands used in the following illus-
trations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered on the first rising edge of DQS follow-
ing the WRITE command, and subsequent data ele-
ments will be registered on successive edges of DQS. The
LOW state on DQS between the WRITE command and
the first rising edge is known as the write preamble; the
LOW state on DQS following the last data-in element
is known as the write postamble.
The time between the WRITE command and the
first corresponding rising edge of DQS (
t
DQSS) is
specified with a relatively wide range (from 75 percent
to 125 percent of one clock cycle). All of the WRITE
diagrams show the nominal case, and where the two
extreme cases (i.e.,
t
DQSS [MIN] and
t
DQSS
[MAX])
might not be intuitive, they have also been included.
Figure 15 shows the nominal case and the extremes of
t
DQSS for a burst of 4. Upon completion of a burst,
assuming no other commands have been initiated, the
DQs will remain High-Z and any additional input data
will be ignored.
Data for any WRITE burst may be concatenated
with or truncated with a subsequent WRITE com-
mand. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the
previous WRITE command. The first data element
from the new burst is applied after either the last
element of a completed burst or the last desired data
element of a longer burst which is being truncated. The
new WRITE command should be issued
x
cycles after
the first WRITE command, where
x
equals the number
of desired data element pairs (pairs are required by the
2
n
-prefetch architecture).
Figure 16 shows concatenated bursts of 4. An ex-
ample of nonconsecutive WRITEs is shown in Figure
17. Full-speed random write accesses within a page or
pages can be performed as shown in Figure 18.
Data for any WRITE burst may be followed by a
subsequent READ command. To follow a WRITE with-
out truncating the WRITE burst,
t
WTR should be met
as shown in Figure 19.
Data for any WRITE burst may be truncated by a
subsequent READ command, as shown in Figure 20.
Note that only the data-in pairs that are registered
prior to the
t
WTR period are written to the internal
Figure 14
WRITE Command
array, and any subsequent data-in should be masked
with DM as shown in Figure 21.
Data for any WRITE burst may be followed by a
subsequent PRECHARGE command. To follow a
WRITE without truncating the WRITE burst,
t
WR
should be met as shown in Figure 22.
Data for any WRITE burst may be truncated by a
subsequent PRECHARGE command, as shown in Fig-
ures 23 and 24. Note that only the data-in pairs that are
registered prior to the
t
WR period are written to the
internal array, and any subsequent data-in should be
masked with DM as shown in Figures 23 and 24. After
the PRECHARGE command, a subsequent command
to the same bank cannot be issued until
t
RP is met.
CS#
WE#
CAS#
RAS#
CKE
CA
A10
BA0,1
HIGH
EN AP
DIS AP
BA
CK
CK#
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON
’
T CARE
x4: A0
–
A9, A11
x8: A0
–
A9
x16: A0
–
A8
x8: A11
x16: A9, A11
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| MT46V32M4TG-75ZL | DOUBLE DATA RATE DDR SDRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M4TG-75L | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75Z | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75ZL | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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