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参数资料
型号： MT46V32M4TG-75L
厂商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 双倍数据速率的DDR SDRAM内存
文件页数： 1/68页
文件大小： 2547K
代理商： MT46V32M4TG-75L
1
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
KEY TIMING PARAMETERS
SPEED
GRADE
-75Z
-75
-8
CLOCK RATE
CL = 2**
133 MHz
100 MHz
100 MHz
DATA-OUT
WINDOW* WINDOW
2.5ns
2.5ns
3.4ns
ACCESS
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.6ns
CL = 2.5**
133 MHz
133 MHz
125 MHz
±0.75ns
±0.75ns
±0.8ns
*Minimum clock rate @ CL = 2 (-75Z and -8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
DOUBLE DATA RATE
(DDR) SDRAM
MT46V32M4 – 8 Meg x 4 x 4 banks
MT46V16M8 – 4 Meg x 8 x 4 banks
MT46V8M16 – 2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
www.micron.com/datasheets
PIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
FEATURES
V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data (x16 has
two – one per byte)
x16 has programmable IOL/IOH option
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
Longer lead TSOP for improved reliability (OCPL)
2.5V I/O (SSTL_2 compatible)
OPTIONS
Configuration
32 Meg x 4
(8 Meg x 4 x 4 banks)
16 Meg x 8
(4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
MARKING
32M4
16M8
8M16
Plastic Package – OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
TG
Timing – Cycle Time
7.5ns @ CL = 2 (DDR266B)
1
7.5ns @ CL = 2.5 (DDR266B)
2
10ns @ CL = 2 (DDR200)
3
-75Z
-75
-8
Self Refresh
Standard
Low Power
none
L
NOTE:
1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
32 Meg x 4
8 Meg x 4 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
2K (A0–A9, A11)
16 Meg x 8
4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
1K (A0–A9)
8 Meg x 16
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
DNU
V
REF
V
SS
UDM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
VssQ
DQ7
NC
V
DD
Q
LDQS
NC
V
DD
DNU
LDM
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
x16
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
x8
x4
V
SS
NC
V
SS
Q
NC
DQ3
V
DD
Q
NC
NC
V
SS
Q
NC
DQ2
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
NC
V
DD
Q
NC
NC
V
DD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
x8
x4
V
DD
NC
V
DD
Q
NC
DQ0
V
SS
Q
NC
NC
V
DD
Q
NC
DQ1
V
SS
Q
NC
NC
V
DD
Q
NC
NC
V
DD
NC
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
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