参数资料
型号: MT46V32M4TG-75L
厂商: Micron Technology, Inc.
英文描述: DOUBLE DATA RATE DDR SDRAM
中文描述: 双倍数据速率的DDR SDRAM内存
文件页数: 35/68页
文件大小: 2547K
代理商: MT46V32M4TG-75L
35
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
Figure 23
WRITE to Precharge
Interrupting
t
DQSS
t
DQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
NOP
PRE
9
NOP
NOP
ADDRESS
Bank
a
,
Col
b
Bank,
(
a
or
all
)
NOP
T0
T1
T2
T3
T2n
T4
T5
NOTE
: 1. DI
b
= data-in for column
b
.
2. Subsequent element of data-in is applied in the programmed order following DI
b
.
3. An interrupted burst of 4 is shown; two data elements are written.
4.tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T2 and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE
command would mask the last two data elements.
9. PRE = PRECHARGE command.
T1n
T6
t
WR
t
RP
DQ
DQS
DM
DI
b
t
DQSS
t
DQSS (MIN)
DQ
DQS
DM
DI
b
t
DQSS
t
DQSS (MAX)
DQ
DQS
DM
DI
b
DON
T CARE
TRANSITIONING DATA
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