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参数资料
| 型号： | MT46V32M4TG-75 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 46/68页 |
| 文件大小： | 2547K |
| 代理商： | MT46V32M4TG-75 |
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46
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
MAX
CAPACITANCE (x4, x8)
(Note: 13; notes appear on pages 50
–
53)
PARAMETER
Delta Input/Output Capacitance: DQs, DQS, DM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
DC
IO
DC
I
1
DC
I
2
C
IO
C
I
1
C
I
2
C
I
3
MIN
–
–
–
4.0
2.0
2.0
2.0
MAX
0.50
0.50
0.25
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
NOTES
24
29
29
I
DD
SPECIFICATIONS AND CONDITIONS (x4, x8)
(Notes: 1
–
5, 10, 12, 14; notes appear on pages 50
–
53) (0
°
C
≤
T
A
≤
+70
°
C; V
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V)
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
cyle; Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); I
OUT
= 0mA; Address and control
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs changing once per
clock cycle.
V
IN
=
V
REF
for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
SYMBOL
-75/-75Z
I
DD
0
-8
100
UNITS
mA
NOTES
22, 48
105
I
DD
1
120
110
mA
22,48
I
DD
2P
3
3
mA
23, 32, 50
I
DD
2F
45
35
mA
51
I
DD
3P
18
18
mA
23, 32, 50
I
DD
3N
45
35
mA
47
I
DD
4R
110
90
mA
22, 48
I
DD
4W
110
90
mA
22
t
RC =
t
RFC (MIN)
t
RC =
15.625μs
Standard
Low power (L)
I
DD
5
I
DD
6
I
DD
7
I
DD
7
I
DD
8
220
5
2
1
325
205
5
3
1
260
mA
mA
mA
mA
mA
22, 50
27, 50
11
11
22,49
SELF REFRESH CURRENT: CKE
≤
0.2V
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
auto precharge,
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control
inputs change only during Active, READ, or WRITE commands.
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相关代理商/技术参数 |
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| MT46V32M4TG-75L | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75Z | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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