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参数资料
| 型号： | MT46V32M4TG-75Z |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 14/68页 |
| 文件大小： | 2547K |
| 代理商： | MT46V32M4TG-75Z |
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14
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
–
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
DESELECT
The DESELECT function (CS# HIGH) prevents new
commands from being executed by the DDR SDRAM.
The DDR SDRAM is effectively deselected. Operations
already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
instruct the selected DDR SDRAM to perform a NOP
(CS# LOW). This prevents unwanted commands from
being registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0-A11.
See mode register descriptions in the Register Defini-
tion section. The LOAD MODE REGISTER command
can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until
t
MRD is met.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A
i
(where
i
= 8 for x16, 9 for x8, or 9, 11 for
x4) selects the starting column location. The value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being ac-
cessed will be precharged at the end of the READ burst;
if auto precharge is not selected, the row will remain
open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
A
i
(where
i
= 8 for x16, 9 for x8, or 9, 11 for x4) selects the
starting column location. The value on input A10 deter-
mines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst; if auto precharge
is not selected, the row will remain open for subsequent
accesses. Input data appearing on the DQs is written to
the memory array subject to the DM input logic level
appearing coincident with the data. If a given DM signal
is registered LOW, the corresponding data will be written
to memory; if the DM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in
all banks. The bank(s) will be available for a subsequent
row access a specified time (
t
RP) after the PRECHARGE
command is issued. Input A10 determines whether one
or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1
select the bank. Otherwise BA0, BA1 are treated as
“
Don
’
t Care.
”
Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A
PRECHARGE command will be treated as a NOP if
there is no open row in that bank (idle state), or if the
previously open row is already in the process of
precharging.
AUTO PRECHARGE
Auto precharge is a feature which performs the
same individual-bank precharge function described
above, but without requiring an explicit command.
This is accomplished by using A10 to enable auto
precharge in conjunction with a specific READ or
WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst. Auto precharge is nonpersistent in that it
is either enabled or disabled for each individual READ
or WRITE command.
Auto precharge ensures that the precharge is initi-
ated at the earliest valid stage within a burst. This
“
earliest valid stage
”
is determined as if an explicit
PRECHARGE command was issued at the earliest pos-
sible time, without violating
t
RAS(MIN), as described
for each burst type in the Operation section of this data
sheet. The user must not issue another command to the
same bank until the precharge time (
t
RP) is completed.
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate READ bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet. The
open page which the READ burst was terminated from
remains open.
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PDF描述 |
|---|---|
| MT46V32M4TG-75ZL | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-8 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-8L | DOUBLE DATA RATE DDR SDRAM |
| MT46V4M32 | DOUBLE DATA RATE DDR SDRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M4TG-75ZL | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-8 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-8L | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M8 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M82ZZ5-75 ES | 制造商:Micron Technology Inc 功能描述:32MX8 SDRAM DDR PLASTIC PBF FBGA 2.5V - Trays |
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