- 您现在的位置：买卖IC网 > PDF目录187166 > MT48LC8M16LFTG-10XT:G 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 PDF资料下载
参数资料
| 型号： | MT48LC8M16LFTG-10XT:G |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 22/79页 |
| 文件大小： | 2760K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页
PDF: 09005aef807f4885/Source: 09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN
29
2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
READs
Figure 15:
Random READ Accesses
Notes:
1. Each READ command may be to either bank. DQM is LOW.
2. BL = 1, 2, 4, 8, or full page (if BL > 1, the following READ interrupts the previous).
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DON’T CARE
DOUT
n
DOUT
a
DOUT
x
DOUT
m
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DQ
DOUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DOUT
a
DOUT
x
DOUT
m
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DQ
DOUT
n
T2
T1
T4
T3
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DOUT
a
DOUT
x
DOUT
m
READ
BANK,
COL a
BANK,
COL x
BANK,
COL m
CL = 1
CL = 2
CL = 3
TRANSITIONING DATA
相关PDF资料 |
PDF描述 |
|---|---|
| MT4C1024DJ-6IT | 1M X 1 FAST PAGE DRAM, 60 ns, PDSO20 |
| MT4LSD232UG-10C1 | 2M X 32 SYNCHRONOUS DRAM MODULE, 7.5 ns, SMA100 |
| MT4S06 | UHF BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
| MT4S104T | UHF BAND, SiGe, NPN, RF SMALL SIGNAL TRANSISTOR |
| MT4S104U | KA BAND, SiGe, NPN, RF SMALL SIGNAL TRANSISTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC8M32B2 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:SYNCHRONOUS DRAM |
发布紧急采购，3分钟左右您将得到回复。