参数资料
型号: MT80C31-30R
厂商: ATMEL CORP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 30 MHz, MICROCONTROLLER, PQFP44
封装: 1 MM HEIGHT, QFP-44
文件页数: 13/170页
文件大小: 4133K
代理商: MT80C31-30R
11
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend-
ing interrupts, as shown in the following example.
Note:
4.7.1
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and
this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt exe-
cution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the
selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program
Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG
is set.
4.8
Register Description
4.8.1
CCP – Configuration Change Protection Register
Bits 7:0 – CCP[7:0] – Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written with the correct
signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction
cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again
by the CPU, and any pending interrupts will be executed according to their priority.
When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is
enabled, while CCP[7:1] will always read as zero.
Table 4-1 shows the signatures that are in recognised.
Assembly Code Example
sei
; set Global Interrupt Enable
sleep
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
Bit
7
6
5432
10
CCP[7:0]
CCP
Read/Write
W
WWWW
WW
R/W
Initial Value
0
0000
00
Table 4-1.
Signatures Recognised by the Configuration Change Protection Register
Signature
Group
Description
0xD8
IOREG: CLKMSR, CLKPSR, WDTCSR
Protected I/O register
相关PDF资料
PDF描述
MV80C31-36D 8-BIT, 36 MHz, MICROCONTROLLER, PQFP44
MS80C51T-30R 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44
MV80C31-30R 8-BIT, 30 MHz, MICROCONTROLLER, PQFP44
MS80C51C-16R 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
MF280C31-30R 8-BIT, 30 MHz, MICROCONTROLLER, PQFP44
相关代理商/技术参数
参数描述
MT80C31BH 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述:
MT80C51BH 制造商:ROCHESTER 制造商全称:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space
MT80C51FB 制造商:Rochester Electronics LLC 功能描述:- Bulk
MT80C51FB/B 制造商:Intel 功能描述:
MT80GB 制造商:Datak Corporation 功能描述: