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Motorola TMOS Power MOSFET Transistor Device Data
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N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
600
Vdc
Drain–to–Gate Voltage (RGS = 1.0 M
)
Gate–to–Source Voltage — Continuous
600
Vdc
— Non–Repetitive (tp
≤
10 ms)
±
20
±
40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100
°
C
— Single Pulse (tp
≤
10
μ
s)
2.0
1.3
7.0
Adc
Apk
Total Power Dissipation @ 25
°
C
Derate above 25
°
C
Total Power Dissipation @ TA = 25
°
C (1)
Operating and Storage Temperature Range
50
0.4
2.5
Watts
W/
°
C
Watts
TJ, Tstg
EAS
– 55 to 150
°
C
mJ
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25
°
C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 2.0 Apk, L = 95 mH, RG = 25
)
Thermal Resistance — Junction to Case
— Junction to Ambient
— Junction to Ambient (1)
190
R
θ
JC
R
θ
JA
R
θ
JA
TL
2.5
62.5
50
°
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″
from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
260
°
C
Preferred
devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTB2N60E/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
2.0 AMPERES
600 VOLTS
RDS(on) = 3.8 OHM
Motorola Preferred Device
CASE 418B–02, Style 2
D2PAK
D
S
G