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参数资料
| 型号： | MTB2P50ET4 |
| 厂商： | MOTOROLA INC |
| 元件分类： | JFETs |
| 英文描述： | 2 A, 500 V, 6 ohm, P-CHANNEL, Si, POWER, MOSFET |
| 文件页数： | 3/10页 |
| 文件大小： | 273K |
| 代理商： | MTB2P50ET4 |
MTB2P50E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(BR)DSS
500
—
564
—
Vdc
mV/
°C
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
—
10
100
Adc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
—
100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)
VGS(th)
2.0
—
3.0
4.0
—
Vdc
mV/
°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.0 Adc)
RDS(on)
—
4.5
6.0
Ohm
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125°C)
VDS(on)
—
9.5
—
14.4
12.6
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)
gFS
1.5
2.9
—
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
—
845
1183
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
—
100
140
Reverse Transfer Capacitance
f = 1.0 MHz)
Crss
—
26
52
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
(VDD = 250 Vdc, ID = 2.0 Adc,
VGS = 10 dc,
RG = 9.1 )
td(on)
—
12
24
ns
Rise Time
(VDD = 250 Vdc, ID = 2.0 Adc,
VGS = 10 dc,
RG = 9.1 )
tr
—
14
28
Turn–Off Delay Time
VGS = 10 dc,
RG = 9.1 )
td(off)
—
21
42
Fall Time
G = 9.1 )
tf
—
19
38
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
QT
—
19
27
nC
(See Figure 8)
(VDS = 400 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
Q1
—
3.7
—
(VDS = 400 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
Q2
—
7.9
—
Q3
—
9.9
—
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
—
2.3
1.85
3.5
—
Vdc
Reverse Recovery Time
(See Figure 14)
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
trr
—
223
—
ns
(See Figure 14)
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
ta
—
161
—
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
tb
—
62
—
Reverse Recovery Stored Charge
QRR
—
1.92
—
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
″ from package to center of die)
LD
—
4.5
—
nH
Internal Source Inductance
(Measured from the source lead 0.25
″ from package to source bond pad)
LS
—
7.5
—
nH
(1) Pulse Test: Pulse Width
≤ 300 s, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
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