参数资料
型号: MX7575JEWN+T
厂商: Maxim Integrated Products
文件页数: 7/12页
文件大小: 0K
描述: IC ADC 8BIT MPU COMP 18-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
位数: 8
采样率(每秒): 200k
数据接口: 并联
转换器数目: 1
功率耗散(最大): 762mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 18-SOIC(0.295",7.50mm 宽)
供应商设备封装: 18-SOIC W
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极
MX7575/MX7576
CMOS, P-Compatible, 5s/10s, 8-Bit ADCs
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
DIP/SO
NAME
FUNCTION
1
CS
Chip Select Input.
CS must be low for the device to be selected or to recognize the RD input.
PIN
2
RD
Read Input.
RD must be low to access data. RD is also used to start conversions. See the
Microprocessor Interface section.
TP
(MX7575)
Test Point. Connect to VDD.
7, 8
D6, D5
Three-State Data Outputs, bits 6 and 5
6
D7
Three-State Data Output, bit 7 (MSB)
5
CLK
External Clock Input/Internal Oscillator Pin for frequency setting RC components.
4
BUSY
BUSY Output. BUSY going low indicates the start of a conversion. BUSY going high indicates the
end of a conversion.
9
DGND
Digital Ground
TA = +25°C
TA = TMIN to TMAX
ALL
J/K/A/B
S/T
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CS to RD Setup Time
t1
0
ns
RD to BUSY Propagation Time
t2
100
120
ns
Data-Access Time after
RD
t3
(Note 6)
100
120
ns
RD Pulse Width
t4
100
120
ns
CS to RD Hold Time
t5
0
ns
Data-Access Time after
BUSY
t6
(Note 6)
80
100
ns
Data-Hold Time
t7
(Note 7)
10
80
10
80
10
100
ns
BUSY to CS Delay
t8
0
ns
TIMING CHARACTERISTICS (Note 5)
(VDD = +5V, VREF = 1.23V, AGND = DGND = 0V.)
Note 5: Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with
tr = tf = 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V.
Note 6: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
PLCC
2
3
4
8, 9
7
6
5
10
3
MODE
(MX7576)
Mode Input. MODE = low puts the ADC into its asynchronous conversion mode. MODE has to be
tied high for the synchronous conversion mode and the ROM interface mode.
14
D0
Three-State Data Output, bit 0 (LSB)
10–13
D4–D1
Three-State Data Outputs, bits 4–1
15
AGND
Analog Ground
16
12–15
17
18
VDD
Power-Supply Voltage. +5V nominal.
17
REF
Reference Input. +1.23V nominal.
N.C.
No Connect
20
19
1, 11
16
AIN
Analog Input. 0V to 2VREF input range.
18
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